Program And Data Memory; Schematic Diagram Of The External Memory Interface - Motorola 56F805 Hardware User Manual

• 56F805 Technical Data, (DSP56F805/D): Provides features list and specifications
including signal descriptions, DC power requirements, AC timing requirements
and available packaging.
Refer to these documents for detailed information about chip functionality and operation.
They can be found on the following URL:

2.2 Program and Data Memory

The 56F805EVM uses one bank of 128K×16-bit Fast Static RAM (GSI GS72116, labeled
U15) for external memory expansion; see the FSRAM schematic diagram in
This physical memory bank is split into two logical memory banks of 64Kx16-bits: one
for Program memory and the other for Data memory. By using the device's program
strobe, PS, signal line, along with the memory chip's A0 signal line, half of the memory
chip is selected when Program memory accesses are requested and the other half of the
memory chip is selected when Data memory accesses are requested. This memory bank
will operate with zero wait-state accesses while the 56F805 is running at 70MHz.
However, when running at 80MHz, the memory bank operates with four wait-state
accesses. This memory bank can be disabled by removing the jumper at JG8.
Figure 2-1. Schematic Diagram of the External Memory Interface
2-4
Freescale Semiconductor, Inc.
http://www.motorola.com/semiconductors
56F805
A0-A15
PS
D0-D15
RD
WR
JG8
Connect Pin 1-2:
Enable SRAM
Jumper Removed:
Disable SRAM
56F805EVM Hardware User's Manual
For More Information On This Product,
Go to: www.freescale.com
GS72116
A1-A16
A0
D0-D15
RD
WR
+3.3V
CS
Figure 2-1.
MOTOROLA