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Board Description and Memory Maps
1
PC87308VUL Super I/O (ISASIO) Strapping
Table 1-16. Strap Pins Configuration for the PC87308VUL
Pins
CFG0
CFG1
CFG3, CFG2
BADDR1, BADDR2
SELCS
NVRAM/RTC & Watchdog Timer Registers
1-32
The PC87308VUL Super I/O (ISASIO) provides the following functions
to the MVME3600/4600 series: a keyboard interface, a PS/2 mouse
interface, a PS/2 floppy port, two async serial ports and a parallel port.
Refer to the PC87308VUL Data Sheet for additional details and
programming information.
The following table shows the hardware strapping for the Super I/O
device:
0 - FDC, KBC and RTC wake up inactive.
1 - Xbus Data Buffer (XDB) enabled.
00 - Clock source is 24 MHz fed via X1 pin.
11 - PnP Motherboard, Wake in Config State. Index $002E.
1 - CS0# on CS0# pin.
The MK48T59/559 provides the MVME3600/4600 series with 8K of non-
volatile SRAM, a time-of-day clock, and a watchdog timer. Accesses to
the MK48T59/559 are accomplished via three registers: The
NVRAM/RTC Address Strobe 0 Register, the NVRAM/RTC Address
Strobe 1 Register, and the NVRAM/RTC Data Port Register. The
NVRAM/RTC Address Strobe 0 Register latches the lower 8 bits of the
address and the NVRAM/RTC Address Strobe 1 Register latches the upper
5 bits of the address.
Reset Configuration
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