Unnormalized (U)—Bit 4; Extension (E)—Bit 5; Limit (L)—Bit 6; Size (Sz)—Bit 7 - Motorola DSP56800 Manual

Program Controller
5.1.8.5 Unnormalized (U)—Bit 4
The unnormalized (U) bit (SR bit 4) is set if the two most significant bits of the most significant product
portion of the result are the same, and is cleared otherwise. The U bit is computed as follows: U = (Bit 31
XOR Bit 30).
If the U bit is cleared, then a positive fractional number, p, satisfies the following relation: 0.5 < p < 1.0. A
negative fractional number, n, it satisfies the following equation: -1.0 < n < -0.5.
This bit is not affected by the OMR's CC bit.
5.1.8.6 Extension (E)—Bit 5
The extension (E) bit (SR bit 5) is cleared if all the bits of the integer portion (bits 35–31) of the 36-bit
result are the same (the upper five bits of the value are 00000 or 11111). Otherwise, this bit is set.
If E is cleared, then the MS and LS portions of an accumulator contain all the bits with information—the
extension register only contains sign extension. In this case, the accumulator extension register can be
ignored. If E is set, then the extension register in the accumulator is in use.
This bit is not affected by the OMR's CC bit.
5.1.8.7 Limit (L)—Bit 6
The limit (L) bit (SR bit 6) is set if the overflow bit is set or if the data limiters perform a limiting
operation; it is not affected otherwise. The L bit is cleared only by a processor reset or an instruction that
specifically clears it. This allows the L bit to be used as a latching overflow bit. Note that L is affected by
data movement operations that read the A or B accumulator registers onto the CGDB.
This bit is not affected by the OMR's CC bit.
5.1.8.8 Size (SZ)—Bit 7
The size (SZ) bit (SR bit 7) is set when moving a 36-bit accumulator to data memory if bits 30 and 29 of
the source accumulator are not the same—that is, if they are not both ones or zeros. This bit is latched, so it
will remain set until the processor is reset or an instruction explicitly clears it.
By monitoring the SZ bit, it is possible to determine whether a value is growing to the point where it will
be saturated or limited when moved to data memory. It is designed for use in the fast Fourier transform
(FFT) algorithm, indicating that the next pass in the algorithm should scale its results before computation.
This allows FFT data to be scaled only on passes where it is necessary instead of on each pass, which in
turn helps guarantee maximum accuracy in an FFT calculation.
5.1.8.9 Interrupt Mask (I1 and I0)—Bits 8–9
The interrupt mask (I1 and I0) bits (SR bits 9 and 8) reflect the current priority level of the DSP core and
indicate the interrupt priority level (IPL) needed for an interrupt source to interrupt the processor. The
current priority level of the processor may be changed under software control. Interrupt mask bit I0 must
always be written with a one to ensure future compatibility and compatibility with other family members.
The interrupt mask bits are set during processor reset. See Table 5-1 on page 5-9 for interrupt mask bit
definitions.
5-8 DSP56800 Family Manual