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Interprocessor Interrupt Dispatch Registers
Offset
Bit
3
3
2
2
1
0
9
8
Name
Operation
R
Reset
$00
There are four Interprocessor Interrupt Dispatch Registers. Writing to an
IPI Dispatch Register with the P0 and/or P1 bit set causes an interprocessor
interrupt request to be sent to one or more processors. Note that each IPI
Dispatch Register has two addresses. These registers are considered to be
per processor registers and there is one address per processor. Reading
these registers returns zeros.
P1
P0
Interrupt Task Priority Registers
Offset
Bit
3
3
2
2
1
0
9
8
Name
Operation
R
Reset
$00
http://www.motorola.com/computer/literature
Processor 0 $20040, $20050, $20060, $20070
Processor 1 $21040, $21050,$21060, $21070
2
2
2
2
2
2
2
2
1
7
6
5
4
3
2
1
0
9
IPI DISPATCH
R
$00
PROCESSOR 1. The interrupt is directed to processor 1.
PROCESSOR 0. The interrupt is directed to processor 0.
Processor 0 $20080
Processor 1 $21080
2
2
2
2
2
2
2
2
1
7
6
5
4
3
2
1
0
9
INTERRUPT TASK PRIORITY
R
$00
Raven Interrupt Controller Implementation
1
1
1
1
1
1
1
1
1
8
7
6
5
4
3
2
1
0 9 8 7 6 5 4 3 2 1 0
R
$00
1
1
1
1
1
1
1
1
1
8
7
6
5
4
3
2
1
0 9 8 7 6 5 4 3 2 1 0
R
$00
R
$00
TP
R
R/W
$0
$F
2-83
2
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