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I
FUNCTIONAL DESCRIPTION
Timer # 1 - User Programmabl e Timer
This programmable timer is not utilized by the MVME135/136 hardware
or on-board firmware and is therefore, available to the user.
Timer #2 - Periodic Tick Timer
When enabled, this timer causes a local Group 3 interrupt on Level 6
when it times out. Group 3, Level 6 ;s the highest local interrupt
except for ABORT. Timer periods range from 1 to
l~
mill iseconds and
are software sel ectabl e.
Timer #3 - Watchdog Timer
This time is capable of generating three types of reset (two local
and one global). The watchdog timer must be periodically serviced
by software to prevent timeout so that the module is not reset.
When a reset does occur, a bit indicating this condition is set in
the local Control/Status Register (CSR) to provide for software
recovery,
if
needed.
A corresponding bit is also set in the
Multiprocessing Control/Status Register (MPCSR) to provide other
bus masters with the reset indication.
Because system controller functions are independent of local reset,
the MVME135/136 modules will not assert the SYSRESET signal on the
VMEbus when either of the local reset options is chosen. Two types
of local reset are available from the watchdog reset timer and are
enabled via bits 6 and 7
(WD~,
WDl) of Local Control Register #5.
They are a r'10mentary Reset of sufficient duration to reset all
hardware on the module, and a Reset And Hold. The momentary reset
option allows the
MC6802~
microprocessor and other devices to come
back up and operate. The reset and hold option keeps the module in
local reset until a SYSRESET is asserted on the VMEbus, or until
another VMEbus master clears the R&H bit in the MPCSR. Both options
are software selectable.
The global reset option for the watchdog timer will cause a
2~0
millisecond minimum reset pulse to appear on the VMEbus SYSRESET
line. This option is also software selectable.
4.15
LOCAL CONTROL/STATUS REGISTERS
The MVME135/136 Control/Status Registers (CSR) use the two
Z8~36
8-
bit parallel ports to provide local and system side information to
the on-board MPU and control of various local and system level
functions.
4-18
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