Interrupt Status Register (Isr) - Motorola DragonBall MC68328 User Manual

System Integration Module
.
31 30 29 28
15 14 13 12
INT7 INT6 INT5 INT4
Address: $(FF)FFF30C
All the interrupt status bits, except IRQs 1, 2, 3, 6, and 7, reflect the interrupt request from
their respective interrupt sources. A status bit is cleared when the interrupt request is
cleared from the requesting module or input pin. Refer to the timer, SPIM, SPIS, RTC, and
PWM sections for details on clearing an interrupt request from those modules. The IRQ7 is
an active low-edge triggered interrupt request. Its status is cleared by writing a 1 to the IRQ7
interrupt status bit. The IRQs 1, 2, 3, and 6 are edge/level programmable. These interrupt
bits are cleared by writing a 1 to the corresponding interrupt status bit if they are pro-
grammed as edge-triggered.
IRQ6
This bit, while set, indicates that an external device is requesting an interrupt on level 6.
If IRQ6 is set to be a level-sensitive interrupt, users must clear the source of the interrupt.
If IRQ6 is set to be an edge-sensitive interrupt, users must clear the interrupt by writing a
1 to this status bit. Writing a 0 to this bit and the other bits of this register has no effect.
0 = No level-6 interrupt pending
1 = Level-6 interrupt pending
UART
This bit, while set, indicates that the UART module needs service. The transmitter might
need data, the receiver might have data ready to transfer to memory, or the CTS or GPIO
pins might have changed state. Each of these interrupts is maskable in the UART control
register. Refer to the UART description for details. This interrupt is a Level 4 interrupt.
0 = No UART service request pending
1 = UART service needed
SPIM
SPIM indicates that a data transfer completed by setting this bit high. Users must clear
this interrupt in the SPI control register. Refer to the SPI section for details. This interrupt
is a Level 4 interrupt.
0 = No SPI master interrupt
1 = SPI master interrupting
PWM
This bit indicates the PWM period rollover. Refer to the PWM section for details. This is a
Level 4 interrupt.
0 = No PWM period rollover
1 = PWM period rolled over
2-14 MC68328 DRAGONBALL PROCESSOR USER'S MANUAL
27 26 25
UNUSED
11 10 9
INT3 INT2 INT1
Figure 2-7. Interrupt Status Register
24 23 22 21
IRQ7 TMR1 SPIS
8 7 6 5
INT0 PWM KB LCDC
20 19 18 17
PEN IRQ6 IRQ3 IRQ2
4 3 2 1
RTC WDT UART TMR2
Reset Value: $00000000
MOTOROLA
16
IRQ1
0
SPIM