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3.2.2.3 NESTED INTERRUPTS.
The following rules apply to nested interrupts:
1. The interrupt controller responds to all EXRQ and INRQ interrupts based
upon their assigned priority level. The highest priority interrupt request
is presented to the M68000 core for servicing. After the vector number
corresponding to this interrupt is passed to the core during an interrupt
acknowledge cycle, this interrupt request is cleared. The remaining in-
terrupt requests, if any, are then assessed by priority so that another
interrupt request may be presented to the core.
2. The 3-bit mask in the M68000 core status register ensures that a sub-
sequent interrupt request at a higher interrupt priority level will suspend
handling of a lower priority interrupt. The 3-bit mask indicates the cur-
rent M68000 priority. Interrupts are inhibited for all priority levels less
than or equal to the current M68000 priority. Priority level 7 cannot be
inhibited by the mask; it is a nonmaskable interrupt level.
3. The interrupt controller allows a higher priority INRQ interrupt to be
presented to the M68000 core before the servicing of a lower priority
INRQ interrupt is completed. This is achieved using the interrupt in-
service register (ISR). Each bit in the ISR corresponds to an INRQ in-
terrupt source.
During an interrupt acknowledge cycle for an INRO interrupt, the in-
service bit is set by the interrupt controller for that interrupt source.
When this bit is set, any subsequent INRO interrupt requests at this
priority level or lower are disabled until servicing of the current interrupt
is completed and the in-service bit is cleared by the user. Pending in-
terrupts for these sources are still set by the corresponding interrupt
pending bit.
Thus, in the interrupt service routine for the INRQ interrupt, the user
can lower the M68000 core mask to level 3 in the status register to allow
higher priority level 4 (INRO) interrupts to generate an interrupt request.
This capability provides nesting of INRO interrupt requests for sources
within level 4. This capability is similar to the way the M68000 core
interrupt mask provides nesting of interrupt requests for the seven in-
terrupt priority levels.
3.2.3 Masking Interrupt Sources and Events
3-22
The user may mask EXRQ and INRQ interrupts to prevent an interrupt request
to the M68000 core. EXRQ interrupt masking is handled external to the IMP
-
e.g., by programming a mask register within an external device. INRQ
interrupt masking is accomplished by programming the IMR. Each bit in the
IMR corresponds to one of 15 INRQ interrupt sources.
MC68302 USER'S MANUAL
MOTOROLA
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