D-27 Cache Management Instructions - Motorola MPC8240 User Manual

Integrated host processor with integrated pci
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Table D-26. Processor Control Instructions (Continued)
mftb
31
mtcrf
31
1
mtmsr
31
2
mtspr
31
Table D-27. Cache Management Instructions
Name
0
5
6
dcbf
31
1
dcbi
31
dcbst
31
dcbt
31
dcbtst
31
dcbz
31
icbi
31
Table D-28. Segment Register Manipulation Instructions
Name
0
5
6
1
mfsr
31
1
mfsrin
31
1
mtsr
31
1
mtsrin
31
Table D-29. Lookaside Buffer Management Instructions
Name
0
5
6
1,4,5
slbia
31
1,4,5
slbie
31
1,5
tlbia
31
1,5
tlbie
31
1,5
tlbsync
31
D
S
0
S
0 0 0 0 0
D
7
8
9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31
0 0 0 0 0
A
0 0 0 0 0
A
0 0 0 0 0
A
0 0 0 0 0
A
0 0 0 0 0
A
0 0 0 0 0
A
0 0 0 0 0
A
7
8
9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31
D
0
SR
D
0 0 0 0 0
S
0
SR
S
0 0 0 0 0
7
8
9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31
0 0 0 0 0
0 0 0 0 0
0 0 0 0 0
0 0 0 0 0
0 0 0 0 0
0 0 0 0 0
0 0 0 0 0
0 0 0 0 0
0 0 0 0 0
0 0 0 0 0
Appendix D. PowerPC Instruction Set Listings
Instructions Grouped by Functional Categories
tpr
CRM
0
0 0 0 0 0
spr
B
B
B
B
B
B
B
0 0 0 0 0
B
0 0 0 0 0
B
0 0 0 0 0
B
0 0 0 0 0
B
0 0 0 0 0
371
0
144
0
146
0
467
0
86
0
470
0
54
0
278
0
246
0
1014
0
982
0
595
0
659
0
210
0
242
0
498
0
434
0
370
0
306
0
566
0
D-25

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