Gci/Idl Interrupts - Motorola DigitalDNA ColdFire MCF5272 User Manual

Integrated microprocessor
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13.2.5 GCI/IDL Interrupts

The PLIC module generates two interrupts—the periodic frame interrupt and the aperiodic
status interrupt.
13.2.5.1 GCI/IDL Periodic Frame Interrupt
The frame interrupt is a periodic 2-KHz interrupt as shown in Figure 13-10. This is the
normal interrupt rate for servicing the incoming and outgoing B and D channels. This
service routine must execute in a timely manner. Each of the B- and D-channel transmit and
receive registers should be written and read prior to the next 2-KHz interrupt for underrun
or overrun conditions to be prevented.
Note that only the active, that is enabled, B- and D-channel receive and transmit registers
need to be read and written. B and D channels which are not active need not have their
receive and transmit registers read and written.
500 µ s
125 µ s
Slot 0
Slot 1
Slot 2
Frame n
2-KHz interrupt
Interrupt service routine
Read Frame n -1 (B&D)
Write Frame n + 1 (B&D)
It should be clear from Figure 13-10 that due to the double buffering through the PLIC
shadow register, frame (n) is written to the PLIC transmit register during the interrupt
service routine of the previous frame, frame (n-1). Similarly on the receive side, frame (n)
is read from the PLIC receive register during the interrupt service routine of the following
frame, frame (n + 2). Figure 13-10 shows that the minimum delay through the PLIC, when
not in loopback mode, is two 2-KHz frames, or 1 mS.
13.2.5.2 GCI Aperiodic Status Interrupt
The aperiodic status interrupt is an interrupt which is driven by a number of conditions. The
CPU services this interrupt by reading the aperiodic status register, ASR, and by reading or
writing the relevant C/I or monitor channel register or registers which have generated this
Slot 3
Slot 0
2-KHz interrupt
Interrupt service routine
Read Frame n (B&D)
Write Frame n + 2 (B&D)
Figure 13-10. Periodic Frame Interrupt
Chapter 13. Physical Layer Interface Controller (PLIC)
Slot 1
Slot 2
Slot 3
Frame n + 1
GCI/IDL Block
Slot 0
Slot 1
Slot 2
Frame n + 2
2-KHz interrupt
Interrupt service routine
Read Frame n + 1 (B&D)
Write Frame n + 3 (B&D)
13-11

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