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7.2 Exception Priority
A hardware priority hierarchy determines which reset or interrupt is serviced first when
simultaneous requests are made. Six sources are not maskable. The remaining sourc-
es are maskable, and the device integration module typically can change the relative
priorities of maskable interrupts. Refer to
terrupt priority and servicing.
The priorities of the unmaskable sources are:
1. RESET pin
2. Clock monitor reset
3. COP watchdog reset
4. XIRQ signal
5. Unimplemented opcode trap
6. Software interrupt instruction (SWI)
An external reset has the highest exception-processing priority, followed by clock
monitor reset, and then the on-chip watchdog reset.
The XIRQ interrupt is pseudo-non-maskable. After reset, the X bit in the CCR is set,
which inhibits all interrupt service requests from the XIRQ pin until the X bit is cleared.
The X bit can be cleared by a program instruction, but program instructions cannot re-
set X from zero to one. Once the X bit is cleared, interrupt service requests made via
the XIRQ pin become non-maskable.
The unimplemented page 2 opcode trap (TRAP) and the software interrupt instruction
(SWI) are special cases. In one sense, these two exceptions have very low priority,
because any enabled interrupt source that is pending prior to the time exception pro-
cessing begins will take precedence. However, once the CPU begins processing a
TRAP or SWI, neither can be interrupted. Also, since these are mutually exclusive in-
structions, they have no relative priority.
All remaining interrupts are subject to masking via the I bit in the CCR. Most M68HC12
MCUs have an external IRQ pin, which is assigned the highest I-bit interrupt priority,
and an internal periodic real-time interrupt generator, which has the next highest pri-
ority. The other maskable sources have default priorities that follow the address order
of the interrupt vectors — the higher the address, the higher the priority of the interrupt.
Other maskable interrupts are associated with on-chip peripherals such as timers or
serial ports. Typically, logic in the device integration module can give one I-masked
source priority over other I-masked sources. Refer to the documentation for the spe-
cific M68HC12 derivative for more information.
7.3 Resets
M68HC12 devices perform resets with a combination of hardware and software. Inte-
gration module circuitry determines the type of reset that has occurred, performs basic
system configuration, then passes control to the CPU12. The CPU fetches a vector
determined by the type of reset that has occurred, jumps to the address pointed to by
the vector, and begins to execute code at that address.
MOTOROLA
7-2
7.4 Interrupts
EXCEPTION PROCESSING
for more detail concerning in-
REFERENCE MANUAL
CPU12
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