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8.7 Interrupt, Checkstop, and Reset Signals
This section describes external interrupts, checks top operations, and hard and soft reset
inputs.
8.7.1 External Interrupts
The external interrupt input signals (INT, SMI and MCP) of the MPC7S0 eventually force
the processor to take the external interrupt vector or the system management interrupt
vector if the MSR[EE] is set, or the machine check interrupt if the MSR[ME] and the
HIDO[EMCP] bits are set.
8.7.2 Checkstops
The MPC7S0 has two checkstop input signals-CKSTP _IN (nonmaskable) and MCP
(enabled when MSR[ME] is cleared, and HIDO[EMCP] is set), and a checkstop output
(CKSTP _OUT) signal. If CKSTP _IN or MCP is asserted, the MPC7S0 halts operations by
gating off all internal clocks. The MPC7S0 asserts CKSTP _OUT if CKSTP _IN is asserted.
If CKSTP _OUT is asserted by the MPC7S0, it has entered the checkstop state, and
processing has halted internally. The CKSTP _OUT signal can be asserted for various
reasons including receiving a TEA signal and detection of external parity errors. For more
information about checks top state, see Section 4.S.2.2, "Checkstop State (MSR[ME]
=
0)."
8.7.3 Reset Inputs
The MPC7S0 has two reset inputs, described as follows:
•
HRESET (hard reset)-The HRESET signal is used for power-on reset sequences,
or for situations in which the MPC7 SO must go through the entire cold start sequence
of internal hardware initializations.
•
SRESET (soft reset)-The soft reset input provides warm reset capability. This
input can be used to avoid forcing the MPC7S0 to complete the cold start sequence.
When either reset input is negated, the processor attempts to fetch code from the system
reset exception vector. The vector is located at offset OxOO 1 00 from the exception prefix (all
zeros or ones, depending on the setting of the exception prefix bit in the machine state
register (MSR[IP]). The MSR[IP] bit is set for HRESET.
8.7.4 System Quiesce Control Signals
The system quiesce control signals (QREQ and QACK) allow the processor to enter the nap
or sleep low-power states, and bring bus activity to a quiescent state in an orderly fashion.
Prior to entering the nap or sleep power state, the MPC7S0 asserts the QREQ signal. This
signal allows the system to terminate or pause any bus activities that are normally snooped.
When the system is ready to enter the system quiesce state, it asserts the QACK signal. At
this time the MPC7S0 may enter a quiescent (low power) state. When the MPC7S0 is in the
quiescent state, it stops snooping bus activity. While the MPC7S0 is in the nap power state,
Chapter 8. System Interface Operation
8-35
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