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Table 8-18. PWM Contrast Control Register Description (Continued)
Name
CCPEN
Contrast Control Enable—This bit is used to enable or dis-
Bit 8
able the contrast control function.
PWx
Pulse Width 7–0—This bit controls the pulse-width of the
Bits 7–0
built-in pulse-width modulator, which controls the contrast of
the LCD screen. See Chapter 15, "Pulse-Width Modulator 1
and 2," for more information.
8.3.19
Refresh Mode Control Register
Only a single bit in this register is used to enable or disable LCD self-refresh mode. The remaining bits are
reserved. The bit assignment for the register is shown in the following register display. The settings for the
bit in the register is listed in Table 8-19.
RMCR
REF_ON
TYPE
RESET
Table 8-19. Refresh Mode Control Register Description
Name
REF_ON
Self-Refresh On—Setting this bit enables the self-refresh
Bit 7
mode of operation with the LCD panel.
Reserved
Reserved
–
Bits 6
0
Note:
On entering self-refresh mode, the LSCLK and LD[7:0] signals stay low. FRM and LP work as normal.
Description
Refresh Mode Control Register
BIT 7
6
rw
0
0
Description
LCD Controller
0 = Contrast control is off.
1 = Contrast control is on.
See description.
5
4
3
0
0
0
0x00
0 = Disable self-refresh mode.
1 = Enter self-refresh mode.
These bits are reserved and should
be set to 0.
Programming Model
Setting
0x(FF)FFFA38
2
1
BIT 0
0
0
0
Setting
8-21
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