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2.1.2.4 Performance Monitor Registers
This section describes the registers used by the performance monitor, which is described in
Chapter
11,
"Performance Monitor."
2.1.2.4.1 Monitor Mode Control Register 0 (MMCRO)
The monitor mode control register 0 (MMCRO), shown in Figure 2-5, is a 32-bit SPR
provided to specify events to be counted and recorded. The MMCRO can be accessed only
in supervisor mode. User-level software can read the contents of MMCRO by issuing an
mfspr instruction to UMMCRO, described in Section 2.1.2.4.2, "User Monitor Mode
Control Register 0 (UMMCRO)."
INTONBITIRANS
~
RTCSELECT
DISCOUNT
ENINT
o
1
2
3
4
5
6
7
8
9 10
PMC21NTCONTROL
PMC11NTCONTROL -
THRESHOLD
PMCTRIGGER
PMC1SELECT
15 16 17 18 19
25 26
Figure 2-5. Monitor Mode Control Register 0 (MMCRO)
PMC2SELECT
31
This register must be cleared at power up. Reading this register does not change its
contents. The bits of the MMCRO register are described in Table 2-7.
Table 2-7. MMCRO Bit Settings
Bit
Name
Description
0
DIS
Disables counting unconditionally
0
The values of the PMCn counters can be changed by hardware.
1
The values of the PMCn counters cannot be changed by hardware.
1
DP
Disables counting while in supervisor mode
0
The PMCn counters can be changed by hardware.
1
If the processor is in supervisor mode (MSR[PR] is cleared), the counters are not
changed by hardware.
2
DU
Disables counting while in user mode
0
The PMCn counters can be changed by hardware.
1
If the processor is in user mode (MSR[PR] is set), the PMCn counters are not
changed by hardware.
3
OMS
Disables counting while MSR[PM] is set
0 The PMCn counters can be changed by hardware.
1 If MSR[PM] is set, the PMCn counters are not changed by hardware.
4
DMR
Disables counting while MSR(PM) is zero.
0
The PMCn counters can be changed by hardware.
1 If MSR[PM] is cleared, the PMCn counters are not changed by hardware.
2-14
MPC750 RISC Microprocessor User's Manual
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