Table of Contents
Advertisement
• Bus Arbitration Logic with Low-Interrupt Latency Support
• Hardware Watchdog
• Low-Power (Standby) Modes
• Freeze Control
3.8.1 System Control Register (SCR)
The SCR is a 32-bit register that consists of system status and control bits,
a bus arbiter control bit, hardware watchdog control bits, low-power control
bits, and freeze select bits. Refer to Figure 3-8 and to the following paragraphs
for a description of each bit in this register. The SCR is a memory-mapped
read-write register. The address of this register is fixed at $0F4 in supervisor
space (FC
=
5).
31
30
$F41o!o
0
I
0
I
IPA
I
HWT
I
WPV
I
ADC
23
22
21
20
19
18
17
16
$F5
I
0
I
0
I
0
I
WPVE
I
RMCST
I
EMWS
I
ADCE
I
BCLM
I
15
14
13
12
11
10
8
$F6
I
FRZW
I
FRZ2
I
FRZl
I
0
I
HWDEN
I
HWDCN2-HWDCNO
7
6
5
$F7
j
LPREC
j
LPPl 6
I
LPEN
I
LOW-POWER CLOCK DIVIDER
Figure 3-8. System Control Register
3.8.2 System Status Bits
The eight most significant bits of the SCR are used to report events recognized
by the system control logic. On recognition of an event, this logic sets the
corresponding bit in the SCR. The bits may be read at any time. A bit is reset
by one and is left unchanged by zero. More than one bit may be reset at a
time.
After system reset (simultaneous assertion of RESET and HALT), these bits
are cleared.
IPA -
Interrupt Priority Active
This bit is set when the M68000 core has an unmasked interrupt request.
When bus clear mask (BCLM) is set, BCLR and the internal bus clear to the
IDMA are asserted.
MOTOROLA
MC68302 USER'S MANUAL
3-47
Advertisement
Table of Contents
