Spi 2 Overview; Figure 13-3 Spi 2 Block Diagram; Table 13-6 Spi 1 Sample Period Control Register Description - Motorola MC68VZ328 User Manual

SPISPC
BIT 15 14
CSRC
TYPE rw rw
0 0
RESET
Table 13-6. SPI 1 Sample Period Control Register Description
Name
CSRC Counter Clock Source—This bit selects the
Bit 15 clock source for the sample period counter.
WAIT Wait—Number of clock periods inserted
Bits 14–0 between data transactions in master mode
13.4

SPI 2 Overview

This section discusses how SPI 2 can be used to communicate with external devices, such as EEPROMs,
analog-to-digital converters, and other peripherals. The SPI 2 module is a 3- or 4-wire system, depending
on whether you are using unidirectional or bidirectional communication mode. It provides the clock for
data transfer and can only function as a master device. It is fully compatible with the serial peripheral
interface on Motorola's 68HC05 and 68HC11 microprocessors. Figure 13-3 shows the SPI 2 block
diagram.
SPI 1 Sample Period Control Register
13 12 11 10 9
rw rw rw rw rw
0 0 0 0 0
Description
MPU Interface
Clock
Control
Generator
Shift Register
MSB
Figure 13-3. SPI 2 Block Diagram
Serial Peripheral Interface 1 and 2
8 7 6 5 4
WAIT
rw rw rw rw rw
0 0 0 0 0
0x0000
0 = SPICLK1 clock
1 = CLK32 (32.68 kHz normal crystal used)
0000 = 0 clocks
0001 = 1 clock
0002 = 2 clocks
.
.
.
7FFF = 32767 clocks (approximately 1 second)
SPICLK2
SPIRXD
SPITXD
SPI 2 Overview
0x(FF)FFF70A
3 2 1 BIT 0
rw rw rw rw
0 0 0 0
Setting
13-11