Cache Reset; Cache Control; Cache Control Register - Motorola MC68030 User Manual

III
On the initial access of a burst operation, a
"retry"
(indicated by the assertion
of
BEAR
and HALT) causes the processor to retry the bus cycle and assert
CBREQ again. However, signaling a retry with simultaneous BERR and HALT
during the second, third, or fourth cycle of a burst operation does not cause
a retry operation, even if the requested operand is misaligned. Assertion of
BERR and HALT during burst fill cycles of a burst operation causes inde-
pendent bus error and halt operations. The processor remains halted until
HALT is negated, and then handles the bus error as described in the previous
paragraphs.
6.2 CACHE RESET
When a hardware reset of the processor occurs, all valid bits of both caches
are cleared. The cache enable bits, burst enable bits, and the freeze bits in
the cache control register (CACR) for both caches .(refer to Figure 6-14) are
also cleared, effectively disabling both caches. The WA bit in the CACR is
also cleared.
6.3 CACHE CONTROL
Only the MC68030 cache control circuitry can directly access the cache arrays,
but the supervisor program can set bits in the CACR to exercise control over
cache operations. The supervisor also has access to the cache address reg-
ister (CAAR), which contains the address for a cache entry to be cleared.
6.3.1 Cache Control Register
6-20
The CACR, shown in Figure 6-14, is a 32-bit register that can be written or
read by the MOVEC instruction or indirectly modified by a reset. Five of the
bits (4-0) control the instruction cache; six other bits (13-8) control the data
cache. Each cache is controlled independently of the other, although a similar
operation can be performed for both caches by a single MOVEC instruction.
For example, loading a long word in which bits 3 and 11 are set into the
CACR clears both caches. Bits 31-14 and 7-5 are reserved for Motorola
definition. They are currently read as zeros and are ignored when written.
For future compatibility, writes should not set these bits.
MC68030 USER'S MANUAL MOTOROLA