System External Cache Control Register (Sxccr) - Motorola MVME3600 Series Programmer's Reference Manual

ROM_A/B_TYP[0:2]
Note

System External Cache Control Register (SXCCR)

The System Cache Control Register is accessed via the RD[32:39] data
lines of the upper Falcon device. This 8-bit register is defined as follows:
REG
BIT 0
FIELD
OPER
RESET 1
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R_A/B_TYP[0:1]
ROM/Flash Type. This field is encoded as follows:
0b000 to 0b101 Reserved
0b110 Intel 16-bit wide Flash with 16K Bottom Boot
Block
0b111 Unknown type (for example, ROM/Flash Sockets)
The device width is different from the width of the Flash bank. If
the bank width is 64-bit and the device width is 16-bit then the
Flash bank consists of four Flash devices.
System External Cache Control Register - $FEF88000
1 2
1 1
SXC_DIS_
System External Cache Enable. When this bit is cleared,
it disables this cache from responding to any bus cycles.
SXC_FLSH_
System External Cache Flush. When this bit
for at least 8 clock
ROM/Flash Type
3 4 5
R/W
1 X X
periods, it causes the system external
Programming Model
6 7
X X
is pulsed true
1-29
1