Register Model; System Clock And Reset Control Register - Motorola MPC823e Reference Manual

5.2 REGISTER MODEL

5.2.1 System Clock and Reset Control Register

The SPLL has a 32-bit control register that is powered by keep-alive power. The system
clock and reset control register (SCCR) is memory-mapped into the MPC823e system
interface unit's register map.
SCCR
BIT 0 1 2
FIELD
RES COM
HRESET
— #
POR
0 0
R/W
R/W R/W
ADDR
BIT 16 17 18
FIELD
RES DFSYNC
HRESET
0 0
POR
0 0
R/W
R/W R/W
ADDR
NOTE: HRESET is hard reset and POR is power-on reset.
= undefined and # = unaffected.
—
* RTDIV depends on the combination of MODCK1and MODCK2. RTSEL depends on MODCK1.
See Table 5-2 for more information.
† This field is set according to the default of the hard reset configuration word.
Bits 0 and 3–5—Reserved
These bits are reserved and must be set to 0.
COM—Clock Output Module
This field controls the output buffer strength of the CLKOUT pin. When both bits are set, the
CLKOUT pin is held in the high state. These bits can be dynamically changed without
generating spikes on the CLKOUT pin. If the CLKOUT pin is not connected to external
circuits, both bits are must be set to minimize noise and power dissipation. The COM field
is cleared by hard reset.
00 = Clock output enabled full-strength buffer.
01 = Clock output enabled half-strength output buffer.
10 = Reserved.
11 = Clock output disabled.
MOTOROLA
3 4 5 6 7
RESERVED TBS RTDIV RTSEL CRQEN PRQEN
0 # #
*
0 0
R/W R/W R/W
(IMMR & 0xFFFF0000) + 0x280
19 20 21 22 23
DFBRG DFNL
0 0
0 0
R/W R/W
(IMMR & 0xFFFF0000) + 0x282
MPC823e REFERENCE MANUAL
Clocks and Power Control
8 9 10 11 12
RESERVED
# 0 0 0
*
0 0 0
R/W R/W R/W R/W
24 25 26 27 28
DFNH DFLCD
0 0
0 0
R/W R/W
13 14 15
EBDF RES
†
0
†
0
R/W R/W
29 30 31
DFALCD
0
0
R/W
5-3