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When a masked INRQ interrupt source has a pending interrupt request, the
corresponding bit is set in the IPR, even though the interrupt is not generated
to the core. By masking all interrupt sources using the IMR, the user may
implement a polling interrupt servicing scheme for INRQ interrupts.
When an INRQ interrupt source from an on-chip peripheral has multiple
interrupt events, the user can individually mask these events by programming
that peripheral mask register. Table 3-3 indicates the interrupt sources that
have multiple interrupt events. In this case, when a masked event occurs, an
interrupt request is not generated for the associated interrupt source, and
the corresponding bit in the IPR is not set. To determine the cause of a pending •
interrupt when an interrupt source has multiple interrupt events, the user
interrupt service routine must read the event register within that on-chip
peripheral.
3.2.4 Interrupt Vector Generation
Pending EXRQ interrupts and unmasked INRQ interrupts are presented to
the M68000 core in order of priority. The M68000 core responds to an interrupt
request by initiating an interrupt acknowledge cycle to receive a vector num-
ber, which allows the core to locate the interrupt's service routine. For INRQ
interrupts, the interrupt controller passes an interrupt
vector
corresponding
to the highest priority, unmasked, pending interrupt. By programming the
GIMR, the user can also enable the interrupt controller to provide the vector
for EXRQ interrupts at levels 1, 6, and 7 (regardless of whether normal or
dedicated mode is selected). The three most significant bits of the interrupt
vector number are programmed by the user in the GIMR. These three bits
are concatenated with five bits generated by the interrupt controller to pro-
vide an 8-bit vector number to the core. The interrupt controller's encoding
of the five low-order bits of the interruot vector is shown in
TrihlA ::l-d
\l\/hi:>n
the core initiates an interrupt acknowledge cycle for level 4 and there is no
internal interrupt pending, the interrupt controller encodes the error code
00000 onto the five low-order bits of the interrupt vector.
3.2.5 Interrupt Controller Programming Model
The user communicates with the interrupt controller using four registers. The
global interrupt mode register (GIMR) defines the interrupt controller's op-
erational mode. The interrupt pending register (IPR) indicates which INRQ
interrupt sources require interrupt service. The interrupt mask register (IMR)
allows the user to prevent any of the INRQ interrupt sources from generating
an interrupt request. The interrupt in-service register (ISR) provides a ca-
pability for nesting INRQ interrupt requests.
MOTOROLA
MC68302 USER'S MANUAL
3-23
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