Status Register; Lea, Pea, And Movem Instruction Execution Times; 10.13 Multiprecision Instruction Execution Times - Motorola M68060 User Manual

Instruction Execution Timing
10.12 LEA, PEA, AND MOVEM EXECUTION TIMES
Table 10-20 indicates the number of clock cycles required for execution of the LEA, PEA,
and MOVEM instructions. The number of operand read and write cycles is shown in paren-
theses (r/w).
Table 10-20. LEA, PEA, and MOVEM Instruction Execution Times
Instruction (An)
LEA 1(0/0)
PEA 1(0/1)
n
MOVEM Mem->Reg
MOVEM Reg->Mem n(0/n)
1
Add 2(1/0) cycles to the (bd,{An,PC},Xi*SF) time for a memory indirect address.
2
"n" is the number of registers being moved.

10.13 MULTIPRECISION INSTRUCTION EXECUTION TIMES

Table 10-21 indicates the number of clock cycles for execution of the multiprecision instruc-
tions. The number of clock cycles includes the time to fetch both operands, perform the
operations, and store the results. The number of read and write cycles is shown in paren-
theses (r/w).
Table 10-21. Multiprecision Instruction Execution Times
Instruction
1
Where <ea>y,<ea>x is (Ay)+,(Ax)+ for CMPM and –(Ay),–(Ax) for all
other instructions.
10.14 STATUS REGISTER, MOVES, AND MISCELLANEOUS
INSTRUCTION EXECUTION TIMES
Table 10-22, Table 10-23, and Table 10-24 indicate the number of clock cycles required for
execution of the status register, MOVES, and miscellaneous instructions. The number of
operand read and write cycles is shown in parentheses (r/w). Where indicated, the number
of clock cycles and r/w cycles must be added to those required for effective address calcu-
lation.
10-22
(An) –
(d16,An)
+ (An)
- - 1(0/0)
- - 2(0/1)
2
n(n/
(n/
- n(n/0)
0)
0)
n(0/
— n(0/n)
n)
Size
ADDX Byte, Word
" Long
CMPM Byte, Word
" Long
SUBX Byte, Word
" Long
ABCD Byte
SBCD Byte
M68060 USER'S MANUAL
(d8,An, (bd,An,
(xxx).WL (d16,PC)
1
Xi∗SF) Xi∗SF)
1(0/0) 2(0/0) 1(0/0)
2(0/1) 3(0/1) 1(0/1)
1+n(n/0) 2+n(n/0) 1+n(n/0)
1+n(0/n) 2+n(0/n) 1+n(0/n)
op Dy,Dx
<ea>y,<ea>x
1(0/0)
1(0/0)
—
—
1(0/0)
1(0/0)
1(0/0)
1(0/0)
(d8,PC, (bd,PC,
Xi∗SF) Xi∗SF)
1(0/0) 1(0/0) 2(0/0)
1(0/1) 2(0/1) 2(0/1)
n(n/0) 1+n(n/0) 2+n(n/0)
— —
op
1
2(2/1)
2(2/1)
2(2/0)
2(2/0)
2(2/1)
2(2/1)
2(2/1)
2(2/1)
MOTOROLA
1
—