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• Automatic buffer filling and emptying. DREQ1 and DREQ2 stay asserted as long as
memory space or data is in the buffers, letting the host load data for the next
operation before the current operation finishes
• Interrupt routing and masking, which lets the host individually detect interrupts
• Interrupt auto-unmask, which lets the controller unmask an interrupt to the host
when an operation finishes
3.3.1 EBI Registers
Table 3-2 describes the controller's seven 32-bit, host-addressable registers that are used to
program MPC180E.
Name
R/W
CSTAT
R/W
Command/Status Register. Used to control global MPC180E functions and to monitor interrupts
(see Section 3.3.1.1, "Command/Status Register (CSTAT)").
ID
R
ID. Gives the fixed ID number unique to the MPC180E (see Section 3.3.1.2, "ID Register").
IMASK
R/W
Interrupt Mask Register. Allows the masking of interrupts to the host (see Section 3.3.1.3, "IMASK
Register").
IBCTL
R/W
Input Buffer Control Register. Contains the starting address in the MPC180E where data from the
input buffer is to be written. Contains the counter mask field (see Section 3.3.1.4, "Input Buffer
Control (IBCTL) and Output Buffer Control (OBCTL) Registers").
IBCNT
R/W
Input Buffer Count Register. Gives the total number of 32-bit words to be written to a specific
execution unit for a given operation. This number is not limited to 128 (4 Kbits), but is the total
number of words to be taken from the input buffer and written to the selected execution unit (see
Section 3.3.1.5, "Input Buffer Count (IBCNT) and Output Buffer Count (OBCNT) Registers").
OBCTL
R/W
Output Buffer Control Register. Contains the starting address in the MPC180E's address map from
where data should be transferred to the output buffer. Also contains the counter mask field (see
Section 3.3.1.4, "Input Buffer Control (IBCTL) and Output Buffer Control (OBCTL) Registers").
OBCNT
R/W
Output Buffer Count Register. Contains the total number of 32-bit words a specific execution unit is
to write to the output buffer for a given operation. This number is not limited to 128 (4 Kbits), but is
the total number of words to be read from the selected (or enabled) execution unit (see
Section 3.3.1.5, "Input Buffer Count (IBCNT) and Output Buffer Count (OBCNT) Registers").
3.3.1.1 Command/Status Register (CSTAT)
CSTAT, shown in Figure 3-2, is used to control the chip software reset and auto-unmask
function and to report interrupt status. The controller synchronizes the software reset
function to the rising edge of MCLK, guaranteeing sufficient setup and hold times.
Chapter 3. External Bus Interface and Memory Map
PRELIMINARY—SUBJECT TO CHANGE WITHOUT NOTICE
Table 3-2. EBI Registers
Description
External Bus Interface
3-5
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