Status Register Format And Functions - Motorola MVME135 User Manual

FUNCTIONAL DESCRIPTION
Switch 54 is a 10-position switch, settable from the front panel.
Switch positions 1 and 2 are control functions (refer to section
3.2.5 for a brief description of these switch functions). Switch
positions 3 through 10 are readable and constitute STAT1 (Status
Register 1) as defined below. In the following text. PA is physical
address, RC is reset condition, (res) is reserved, and NA is not
available for use.
4.15.1 Status Register Format And Functions
The following text describes the format and functions of the Status
Registers.
<STAT1> Physical Address: SFFFB000D (Read Only)
RC
=
None
007 006
DOS
004 003 002 001 000
GP7 GP6
GP5 GP4 GP3 GP2 GP1 GPO
84·3 84·4 84·5
84·6
84-7
S4-8 84·9 84·10
GP7-GP0 < General Purpose User Status Bits>
GP0 through GP7 are front panel selectable user status bits (54-3
through 54-10) used for software steering. Access to this register
will read Port A of the timer. 135bug configures Port A of the
timer as an input port and uses these general purpose bits to
perform various optional switching functions. For a complete
description of 135bug' s use of these switches, refer to the 135bug
Diagnostic/Debug Package User's Manual.
If firmware other than 135bug is used, the resident firmware must
configure Port A of the timer before reading STAT!, otherwise, the
data will not be a valid representation of the switch settings.
Refer to the Zilog Z-CIO (Z8036) Counter/Timer and Parallel I/O
Unit Technical Manual for information on programming the timer
registers.
<STAT2> Physical Address: SFFFB0032 (Read Only)
RC
=
Not Valid
007 006 005 004 003 002 001 000
I
RAMERR"IRMCERR"I ABORT" 18Y8FAIL'1 VBER" I VSBERR" IMMUBEWI LCLERR·I
Data bits 00, 01, 02, 03, 06, and 07 will clear automatically when
read. These six data bits will indicate the bus error that is the
most recent only. The contents of this register is invalid after
4·19
I