Interrupt Vector Register (Ivr) - Motorola DragonBall MC68328 User Manual

System Integration Module
interrupt-acknowledge cycle. The interrupt controller generates a vector and presents it to
the core, which then jumps to the interrupt-service routine. If the core is in an interrupt-ser-
vice routine and a higher priority interrupt is posted, the process repeats and the higher pri-
ority is serviced. Interrupt priority is based on the interrupt level. Interrupts with the same
interrupt level are prioritized by the software during the execution of the interrupt-service
routine. The MC68328 processor provides one interrupt vector for each interrupt level. The
most significant 5 bits of the interrupt vector are user-programmable while the lower 3 bits
reflect the interrupt level being serviced.
All interrupts are maskable. Writing a 1 to a bit in the interrupt-mask register disables that
interrupt. If an interrupt is masked, its status is accessible in the interrupt-pending register.
2.3.2 Programmer's Model
This section describes the bits and registers that control the interrupt module. All unused bits
may be written with no effect. When they are read, they indicate 0.
2.3.2.1 INTERRUPT VECTOR REGISTER (IVR). This register programs the upper 5 bits of
the interrupt vector.During the interrupt-acknowledge cycle, the lower 3 bits encode the
interrupt level.
If the interrupt-vector register is never programmed and an inter-
rupt occurs, the interrupt vector $0F is returned to indicate an
uninitialized interrupt.
2.3.2.2 VECTOR GENERATOR. The interrupt controller block provides a vector to the
MC68EC000 core. Users have access to the upper 5 bits of the vector to place the vector
table anywhere in the vector space. Coding for the vectors is as follows:
2-8 MC68328 DRAGONBALL PROCESSOR USER'S MANUAL
7 6 5 4
VECTOR
Address: $(FF)FFF300
Figure 2-5. Interrupt Control Register
NOTE
Table 2-1. Interrupt Vectors
Interrupt
level 7
level 6
level 5
level 4
level 3
level 2
level 1
3 2 1 0
0 0 0
Reset Value: $00
Vector
xxxxx111
xxxxx110
xxxxx101
xxxxx100
xxxxx011
xxxxx010
xxxxx001
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