Peripheral Control And Status Registers - Motorola MPC8240 User Manual

Integrated host processor with integrated pci
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Local Memory Map
0
2G
EUMBBAR
EUMBBAR+1MB-1
4G-32M
4G
Figure 3-12. Embedded Utilities Memory Block Mapping to Local Memory
Table 3-12 summarizes the embedded utilities local memory registers and their offsets.
Table 3-12. Embedded Utilities Local Memory Register Summary
Local Memory Offset
0x0_0000 - 0x0_0FFF
0x0_1000 – 0x0_1FFF
0x0_2000 – 0x0_2FFF
0x0_3000 – 0x0_3FFF
0x0_4000 – 0x3_FFFF
0x4_0000 – 0x7_FFFF
0x8_0000 – 0xF_EFFF
0xF_F000 – 0xF_F017
0xF_F018 – 0xF_F048
0xF_F04D – 0xF_FFFF

3.4.2 Peripheral Control and Status Registers

The MPC8240 contains a set of memory mapped registers that are accessible from the PCI
bus in both host and agent mode. These registers allow external masters on the PCI bus to
access the MPC8240's on-chip embedded utilities such as the message unit, DMA
Register Set
Message registers,
Doorbell interface, I
O
2
DMA controller
ATU
2
I
C controller
Reserved
EPIC controller
Reserved
Data path diagnostics
Data path diagnostics
(watchpoint registers)
Reserved
Chapter 3. Address Maps
Embedded Utilities Memory Block (EUMB)
Embedded Utilities
Memory Block
0x0_0000
0x0_1000
0x0_2000
0x0_3000
0x0_4000
0x4_0000
0x8_0000
0xF _ F000
0xF _ F048
0xF _ FFFF
Shaded area indicates locations not
allowed for the EUMB.
Reference
Section 9.2.1, "Message and Doorbell Register Summary"
and Section 9.3.2, "I2O Register Summary"
Section 8.2, "DMA Register Summary"
Section 3.3.3, "Address Translation Registers"
Section 10.3, "I2C Register Descriptions"
Section 11.2, "EPIC Register Summary"
Section 15.1, "Debug Register Summary"
Chapter 16, "Programmable I/O and Watchpoint"
Message Unit
DMA
ATU
2
I
C
EPIC
Diagnostic
Registers
Data path
diagnostics
3-19

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