Gpiomis Register; Gpiomis Register Field Descriptions - Texas Instruments CC3235 SimpleLink Series Technical Reference Manual

www.ti.com
5.5.8 GPIOMIS Register (offset = 418h) [reset = 0h]
GPIOMIS is shown in
The GPIOMIS register is the masked interrupt status register. If a bit is set in this register, the
corresponding interrupt has triggered an interrupt to the interrupt controller. If a bit is clear, either no
interrupt has been generated, or the interrupt is masked.
GPIOMIS is the state of the interrupt after masking.
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10
Bit Field
31-8 RESERVED
7-0 MIS
SWRU543 – January 2019
Submit Documentation Feedback
Figure 5-11 and described in
Figure 5-11. GPIOMIS Register
RESERVED
R-0h
Table 5-11. GPIOMIS Register Field Descriptions
Type Reset
R 0h
R 0h
Copyright © 2019, Texas Instruments Incorporated
Table 5-11.
9
Description
GPIO Masked Interrupt Status
For edge-detect interrupts, this bit is cleared by writing a 1 to the
corresponding bit in the GPIOICR register. For a GPIO level-detect
interrupt, the bit is cleared when the level is deasserted.
0h = An interrupt condition on the corresponding pin is masked or
has not occurred.
1h = An interrupt condition on the corresponding pin has triggered an
interrupt to the interrupt controller.
General-Purpose Input/Outputs (GPIOs)
GPIO Registers
8 7 6 5 4 3 2 1
MIS
R-0h
0
169