Texas Instruments TMS320 2806 Series Technical Reference Manual

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TMS320x2806x Microcontrollers

Technical Reference Manual

Literature Number: SPRUH18I

JANUARY 2011 – REVISED JUNE 2022

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Page 1 TMS320x2806x Microcontrollers Technical Reference Manual Literature Number: SPRUH18I JANUARY 2011 – REVISED JUNE 2022...
Page 3 1.7.1 On-chip Voltage Regulator (VREG).........................193 1.7.2 On-chip Power-On Reset (POR) and Brown-Out Reset (BOR) Circuit..............2 Boot ROM.................................... 2.1 Boot ROM Memory Map..............................SPRUH18I – JANUARY 2011 – REVISED JUNE 2022 TMS320x2806x Microcontrollers Submit Document Feedback Copyright © 2022 Texas Instruments Incorporated...
Page 4 3.3.10 Controlling a Peak Current Mode Controlled Buck Module................... 3.3.11 Controlling H-Bridge LLC Resonant Converter......................326 3.4 Registers..................................3.4.1 Time-Base Submodule Registers..........................3.4.2 Counter-Compare Submodule Registers........................ TMS320x2806x Microcontrollers SPRUH18I – JANUARY 2011 – REVISED JUNE 2022 Submit Document Feedback Copyright © 2022 Texas Instruments Incorporated...
Page 5 6.4.4 32-Bit Counter and Phase Control...........................437 6.4.5 CAP1-CAP4 Registers............................6.4.6 Interrupt Control...............................438 6.4.7 DMA Interrupt................................6.4.8 Shadow Load and Lockout Control......................... 6.4.9 APWM Mode Operation............................440 SPRUH18I – JANUARY 2011 – REVISED JUNE 2022 TMS320x2806x Microcontrollers Submit Document Feedback Copyright © 2022 Texas Instruments Incorporated...
Page 6 8.10.1 Internal Reference Voltage............................ 8.10.2 External Reference Voltage...........................527 8.11 ADC Timings................................8.12 Internal Temperature Sensor............................532 8.12.1 Transfer Function..............................532 8.13 ADC Registers................................TMS320x2806x Microcontrollers SPRUH18I – JANUARY 2011 – REVISED JUNE 2022 Submit Document Feedback Copyright © 2022 Texas Instruments Incorporated...
Page 7 10.6.2 Addressing Modes and Encoding..........................589 10.6.3 Instructions................................10.7 CLA Registers................................10.7.1 Register Memory Mapping............................ 10.7.2 Task Interrupt Vector Registers..........................10.7.3 Configuration Registers............................SPRUH18I – JANUARY 2011 – REVISED JUNE 2022 TMS320x2806x Microcontrollers Submit Document Feedback Copyright © 2022 Texas Instruments Incorporated...
Page 8 12.3.6 SPI Clocking Schemes............................12.3.7 SPI FIFO Description.............................772 12.3.8 SPI 3-Wire Mode Description..........................12.4 Programming Procedure.............................. 12.4.1 Initialization Upon Reset............................775 12.4.2 Configuring the SPI............................... TMS320x2806x Microcontrollers SPRUH18I – JANUARY 2011 – REVISED JUNE 2022 Submit Document Feedback Copyright © 2022 Texas Instruments Incorporated...
Page 9 14.3.9 Digital Loopback Mode............................14.3.10 NACK Bit Generation............................850 14.4 Interrupt Requests Generated by the I2C Module....................... 14.4.1 Basic I2C Interrupt Requests..........................851 SPRUH18I – JANUARY 2011 – REVISED JUNE 2022 TMS320x2806x Microcontrollers Submit Document Feedback Copyright © 2022 Texas Instruments Incorporated...
Page 10 15.7.16 Set the Receive Frame-Synchronization Polarity....................15.7.17 Set the Receive Clock Mode..........................15.7.18 Set the Receive Clock Polarity..........................15.7.19 Set the SRG Clock Divide-Down Value....................... TMS320x2806x Microcontrollers SPRUH18I – JANUARY 2011 – REVISED JUNE 2022 Submit Document Feedback Copyright © 2022 Texas Instruments Incorporated...
Page 11 (CANMD)........................1025 16.9.3 Transmission-Request Set Register (CANTRS)....................1026 16.9.4 Transmission-Request-Reset Register (CANTRR)..................... 1027 16.9.5 Transmission-Acknowledge Register (CANTA)....................1027 16.9.6 Abort-Acknowledge Register (CANAA)....................... 1028 SPRUH18I – JANUARY 2011 – REVISED JUNE 2022 TMS320x2806x Microcontrollers Submit Document Feedback Copyright © 2022 Texas Instruments Incorporated...
Page 12 17.5.31 USB Type Endpoint 0 Register (USBTYPE0), offset 0x10A................1107 17.5.32 USB NAK Limit Register (USBNAKLMT), offset 0x10B..................1108 17.5.33 USB Transmit Control and Status Endpoint n Low Register (USBTXCSRL[1]-USBTXCSRL[3).......1109 TMS320x2806x Microcontrollers SPRUH18I – JANUARY 2011 – REVISED JUNE 2022 Submit Document Feedback Copyright © 2022 Texas Instruments Incorporated...
Page 13 Figure 1-33. EPWM DMA/CLA Configuration (EPWMCFG) Register..................Figure 1-34. Clocking and Reset Logic............................85 Figure 1-35. Clock Fail Interrupt..............................Figure 1-36. NMI Configuration (NMICFG) Register......................... SPRUH18I – JANUARY 2011 – REVISED JUNE 2022 TMS320x2806x Microcontrollers Submit Document Feedback Copyright © 2022 Texas Instruments Incorporated...
Page 14 Figure 1-95. Reset Flow Diagram............................171 Figure 1-96. PIE Interrupt Sources and External Interrupts XINT1/XINT2/XINT3..............Figure 1-97. Multiplexed Interrupt Request Flow Diagram...................... TMS320x2806x Microcontrollers SPRUH18I – JANUARY 2011 – REVISED JUNE 2022 Submit Document Feedback Copyright © 2022 Texas Instruments Incorporated...
Page 15 Figure 3-19. Action-Qualifier Submodule Inputs and Outputs....................Figure 3-20. Possible Action-Qualifier Actions for EPWMxA and EPWMxB Outputs..............267 Figure 3-21. Up-Down-Count Mode Symmetrical Waveform....................270 SPRUH18I – JANUARY 2011 – REVISED JUNE 2022 TMS320x2806x Microcontrollers Submit Document Feedback Copyright © 2022 Texas Instruments Incorporated...
Page 16 Figure 3-76. Time-Base Counter Register (TBCTR)........................332 Figure 3-77. Time-Base Period Register (TBPRD)........................332 Figure 3-78. Time Base Period High Resolution Register (TBPRDHR).................. TMS320x2806x Microcontrollers SPRUH18I – JANUARY 2011 – REVISED JUNE 2022 Submit Document Feedback Copyright © 2022 Texas Instruments Incorporated...
Page 17 Figure 5-4. HCCOUNTER Behavior During High Pulse Width Capture.................. Figure 5-5. Rise versus Fall Capture Events........................... Figure 5-6. High Pulse Width Normal Mode Capture......................SPRUH18I – JANUARY 2011 – REVISED JUNE 2022 TMS320x2806x Microcontrollers Submit Document Feedback Copyright © 2022 Texas Instruments Incorporated...
Page 18 Figure 7-16. Unit Position Event for Low Speed Measurement (QCAPCTL[UPPS] = 0010)...........480 Figure 7-17. eQEP Edge Capture Unit - Timing Details......................Figure 7-18. eQEP Watchdog Timer............................482 TMS320x2806x Microcontrollers SPRUH18I – JANUARY 2011 – REVISED JUNE 2022 Submit Document Feedback Copyright © 2022 Texas Instruments Incorporated...
Page 19 Figure 8-33. ADC SOC0-SOC15 Control Registers (ADCSOCxCTL)..................553 Figure 8-34. ADC Reference/Gain Trim Register (ADCREFTRIM)..................Figure 8-35. ADC Offset Trim Register (ADCOFFTRIM)......................556 SPRUH18I – JANUARY 2011 – REVISED JUNE 2022 TMS320x2806x Microcontrollers Submit Document Feedback Copyright © 2022 Texas Instruments Incorporated...
Page 20 Figure 11-27. Shadow Destination Begin and Current Address Pointer Registers (SRC_ADDR_SHADOW/ DST_ADDR_SHADOW)...............................758 Figure 11-28. Active Destination Begin and Current Address Pointer Registers (SRC_ADDR/DST_ADDR)......Figure 12-1. SPI CPU Interface............................... TMS320x2806x Microcontrollers SPRUH18I – JANUARY 2011 – REVISED JUNE 2022 Submit Document Feedback Copyright © 2022 Texas Instruments Incorporated...
Page 21 Figure 14-13. Repeated START Condition (in This Case, 7-Bit Addressing Format).............. Figure 14-14. Synchronization of Two I2C Clock Generators During Arbitration..............847 Figure 14-15. Arbitration Procedure Between Two Master-Transmitters.................848 SPRUH18I – JANUARY 2011 – REVISED JUNE 2022 TMS320x2806x Microcontrollers Submit Document Feedback Copyright © 2022 Texas Instruments Incorporated...
Page 22 Figure 15-41. SPI Interface with McBSP Used as Master....................... Figure 15-42. SPI Interface With McBSP Used as Slave......................Figure 15-43. Unexpected Frame-Synchronization Pulse With (R/X)FIG = 0................. TMS320x2806x Microcontrollers SPRUH18I – JANUARY 2011 – REVISED JUNE 2022 Submit Document Feedback Copyright © 2022 Texas Instruments Incorporated...
Page 23 1006 Figure 16-5. Initialization Sequence............................1011 Figure 16-6. CAN Bit Timing..............................1012 Figure 16-7. Interrupts Scheme............................. 1018 Figure 16-8. Local-Acceptance-Mask Register (LAMn)......................1024 SPRUH18I – JANUARY 2011 – REVISED JUNE 2022 TMS320x2806x Microcontrollers Submit Document Feedback Copyright © 2022 Texas Instruments Incorporated...
Page 24 Figure 17-26. USB Low-Speed Last Transaction to End of Frame Timing Register (USBLSEOF)........1094 Figure 17-27. USB Transmit Functional Address Endpoint n Registers (USBTXFUNCADDR[n])........1095 TMS320x2806x Microcontrollers SPRUH18I – JANUARY 2011 – REVISED JUNE 2022 Submit Document Feedback Copyright © 2022 Texas Instruments Incorporated...
Page 25 Table 1-18. Peripheral Clock Control 3 Register (PCLKCR3) Field Descriptions..............Table 1-19. Low-Speed Peripheral Clock Prescaler Register (LOSPCP) Field Descriptions............ Table 1-20. Internal Oscillator n Trim (INTOSCnTRIM) Register Field Descriptions..............SPRUH18I – JANUARY 2011 – REVISED JUNE 2022 TMS320x2806x Microcontrollers Submit Document Feedback Copyright © 2022 Texas Instruments Incorporated...
Page 26 Table 1-79. GPIO Port A Direction (GPADIR) Register Field Descriptions................Table 1-80. GPIO Port B Direction (GPBDIR) Register Field Descriptions................143 Table 1-81. Analog I/O DIR (AIODIR) Register Field Descriptions..................TMS320x2806x Microcontrollers SPRUH18I – JANUARY 2011 – REVISED JUNE 2022 Submit Document Feedback Copyright © 2022 Texas Instruments Incorporated...
Page 27 Table 2-9. General Structure Of Source Program Data Stream In 16-Bit Mode..............Table 2-10. LSB/MSB Loading Sequence in 8-Bit Data Stream....................SPRUH18I – JANUARY 2011 – REVISED JUNE 2022 TMS320x2806x Microcontrollers Submit Document Feedback Copyright © 2022 Texas Instruments Incorporated...
Page 28 Table 3-51. Event-Trigger Prescale Register (ETPS) Field Descriptions.................360 Table 3-52. Event-Trigger Flag Register (ETFLG) Field Descriptions..................Table 3-53. Event-Trigger Clear Register (ETCLR) Field Descriptions..................363 TMS320x2806x Microcontrollers SPRUH18I – JANUARY 2011 – REVISED JUNE 2022 Submit Document Feedback Copyright © 2022 Texas Instruments Incorporated...
Page 29 Table 7-10. QPOSILAT Register Field Descriptions........................ Table 7-11. QPOSSLAT Register Field Descriptions....................... Table 7-12. QPOSLAT Register Field Descriptions......................... Table 7-13. QUTMR Register Field Descriptions........................488 SPRUH18I – JANUARY 2011 – REVISED JUNE 2022 TMS320x2806x Microcontrollers Submit Document Feedback Copyright © 2022 Texas Instruments Incorporated...
Page 30 Table 10-5. INSTRUCTION dest, source1, source2 Short Description................... Table 10-6. Addressing Modes..............................Table 10-7. Shift Field Encoding.............................. Table 10-8. Operand Encoding..............................TMS320x2806x Microcontrollers SPRUH18I – JANUARY 2011 – REVISED JUNE 2022 Submit Document Feedback Copyright © 2022 Texas Instruments Incorporated...
Page 31 Table 12-5. 3-Wire SPI Pin Configuration..........................Table 12-6. SPI Base Address Table............................Table 12-7. SPI_REGS Registers............................779 Table 12-8. SPI_REGS Access Type Codes........................... SPRUH18I – JANUARY 2011 – REVISED JUNE 2022 TMS320x2806x Microcontrollers Submit Document Feedback Copyright © 2022 Texas Instruments Incorporated...
Page 32 Table 15-4. Effects of DLB and CLKSTP on Clock Modes...................... Table 15-5. Choosing an Input Clock for the Sample Rate Generator with the SCLKME and CLKSM Bits......TMS320x2806x Microcontrollers SPRUH18I – JANUARY 2011 – REVISED JUNE 2022 Submit Document Feedback Copyright © 2022 Texas Instruments Incorporated...
Page 33 Table 15-65. Register Bits Used to Set SRG Frame-Synchronization Period and Pulse Width..........Table 15-66. Register Bit Used to Set the Transmit Clock Mode.....................952 SPRUH18I – JANUARY 2011 – REVISED JUNE 2022 TMS320x2806x Microcontrollers Submit Document Feedback Copyright © 2022 Texas Instruments Incorporated...
Page 34 Table 16-21. Global Interrupt Flag Registers (CANGIF0/CANGIF1) Field Descriptions............1042 Table 16-22. Global Interrupt Mask Register (CANGIM) Field Descriptions................1043 Table 16-23. Mailbox Interrupt Mask Register (CANMIM) Field Descriptions................1044 TMS320x2806x Microcontrollers SPRUH18I – JANUARY 2011 – REVISED JUNE 2022 Submit Document Feedback Copyright © 2022 Texas Instruments Incorporated...
Page 35 Table 17-45. USB Transmit Control and Status Endpoint n High Register (USBTXCSRH[n]) in Device Mode Field Descriptions..................................1113 Table 17-46. USB Maximum Receive Data Endpoint n Registers (USBTXMAXP[n]) Field Descriptions......1114 SPRUH18I – JANUARY 2011 – REVISED JUNE 2022 TMS320x2806x Microcontrollers Submit Document Feedback Copyright © 2022 Texas Instruments Incorporated...
Page 36 Table 17-68. USB General-Purpose Control and Status Register (USBGPCS) Field Descriptions........1136 Table 17-69. USB DMA Select Register (USBDMASEL) Field Descriptions................. 1137 TMS320x2806x Microcontrollers SPRUH18I – JANUARY 2011 – REVISED JUNE 2022 Submit Document Feedback Copyright © 2022 Texas Instruments Incorporated...
Page 37 This glossary lists and explains terms, acronyms, and definitions. Related Documentation From Texas Instruments For a complete listing of related documentation and development-support tools for these devices, visit the Texas Instruments website at http://www.ti.com. Additionally, the TMS320C28x DSP CPU and Instruction Set Reference Guide...
Page 38 Read This First www.ti.com All trademarks are the property of their respective owners. TMS320x2806x Microcontrollers SPRUH18I – JANUARY 2011 – REVISED JUNE 2022 Submit Document Feedback Copyright © 2022 Texas Instruments Incorporated...
Page 39: Table Of Contents
1.1 Flash and OTP Memory Blocks..........................40 1.2 Code Security Module (CSM).............................52 Clocking..................................62 1.4 General-Purpose Input/Output (GPIO)........................107 1.5 Peripheral Frames..............................1.6 Peripheral Interrupt Expansion (PIE)........................167 VREG/BOR/POR................................193 SPRUH18I – JANUARY 2011 – REVISED JUNE 2022 TMS320x2806x Microcontrollers Submit Document Feedback Copyright © 2022 Texas Instruments Incorporated...
Page 40: Flash And Otp Memory Blocks
Thus, the OTP can be used to program data or code. This block, unlike flash, can be programmed only one time and cannot be erased. TMS320x2806x Microcontrollers SPRUH18I – JANUARY 2011 – REVISED JUNE 2022 Submit Document Feedback Copyright © 2022 Texas Instruments Incorporated...
Page 41 If any access to the flash/OTP memory occurs during this delay the CPU automatically stalls until the delay is complete. SPRUH18I – JANUARY 2011 – REVISED JUNE 2022 TMS320x2806x Microcontrollers Submit Document Feedback Copyright © 2022 Texas Instruments Incorporated...
Page 42 FBANKWAIT register. The number of wait states used by a random access is controlled by the RANDWAIT bits and the number of wait states used by a paged access is controlled by the PAGEWAIT bits. The TMS320x2806x Microcontrollers SPRUH18I – JANUARY 2011 – REVISED JUNE 2022 Submit Document Feedback Copyright © 2022 Texas Instruments Incorporated...
Page 43 Using this technique, the overall efficiency of sequential code execution from flash or OTP is improved significantly. SPRUH18I – JANUARY 2011 – REVISED JUNE 2022 TMS320x2806x Microcontrollers Submit Document Feedback Copyright © 2022 Texas Instruments Incorporated...
Page 44 2. Addresses from 0x3F 7FF0 to 0x3F 7FF5 are reserved for data variables and should not contain program code. TMS320x2806x Microcontrollers SPRUH18I – JANUARY 2011 – REVISED JUNE 2022 Submit Document Feedback Copyright © 2022 Texas Instruments Incorporated...
Page 45 Return to calling function SARAM, Flash, Continue execution or OTP Figure 1-3. Flash Configuration Access Flow Diagram SPRUH18I – JANUARY 2011 – REVISED JUNE 2022 TMS320x2806x Microcontrollers Submit Document Feedback Copyright © 2022 Texas Instruments Incorporated...
Page 46 Read access is always available. The registers can be accessed through the JTAG port without the need to execute EALLOW. See Section 1.5.2 for information on EALLOW protection. These registers support both 16-bit and 32-bit accesses. TMS320x2806x Microcontrollers SPRUH18I – JANUARY 2011 – REVISED JUNE 2022 Submit Document Feedback Copyright © 2022 Texas Instruments Incorporated...
Page 47 Section 1.5.2 for more information. This register is protected by the Code Security Module (CSM). See Section 1.2 for more information. SPRUH18I – JANUARY 2011 – REVISED JUNE 2022 TMS320x2806x Microcontrollers Submit Document Feedback Copyright © 2022 Texas Instruments Incorporated...
Page 48 Section 1.5.2 for more information. This register is protected by the Code Security Module (CSM). See Section 1.2 for more information. TMS320x2806x Microcontrollers SPRUH18I – JANUARY 2011 – REVISED JUNE 2022 Submit Document Feedback Copyright © 2022 Texas Instruments Incorporated...
Page 49 Section 1.5.2 for more information. This register is protected by the Code Security Module (CSM). See Section 1.2 for more information. SPRUH18I – JANUARY 2011 – REVISED JUNE 2022 TMS320x2806x Microcontrollers Submit Document Feedback Copyright © 2022 Texas Instruments Incorporated...
Page 50 This register is protected by the Code Security Module (CSM). See Section 1.2 for more information. When writing to this register, follow the procedure described in Section 1.1.3.4. TMS320x2806x Microcontrollers SPRUH18I – JANUARY 2011 – REVISED JUNE 2022 Submit Document Feedback Copyright © 2022 Texas Instruments Incorporated...
Page 51 This register is protected by the Code Security Module (CSM). See Section 1.2 for more information. When writing to this register, follow the procedure described in Section 1.1.3.4. SPRUH18I – JANUARY 2011 – REVISED JUNE 2022 TMS320x2806x Microcontrollers Submit Document Feedback Copyright © 2022 Texas Instruments Incorporated...
Page 52: Code Security Module (Csm)
Section 1.2.3.2. Using a password of all zeros will seriously limit your ability to debug secure code or reprogram the flash. TMS320x2806x Microcontrollers SPRUH18I – JANUARY 2011 – REVISED JUNE 2022 Submit Document Feedback Copyright © 2022 Texas Instruments Incorporated...
Page 53 Addresses 0x3F 7FF0 through 0x3F 7FF5 are reserved for data variables and should not contain program code. SPRUH18I – JANUARY 2011 – REVISED JUNE 2022 TMS320x2806x Microcontrollers Submit Document Feedback Copyright © 2022 Texas Instruments Incorporated...
Page 54 The Code Security Module ( CSM ) included on this device was designed to password protect the data stored in the associated memory and is warranted by Texas Instruments (TI), in accordance with its standard terms and conditions, to conform to TI's published specifications for the warranty period applicable for this device.
Page 55 A password is not needed to run the code out of secure memory (such as in end-customer usage); however, access to secure memory contents for debug purpose requires a password. SPRUH18I – JANUARY 2011 – REVISED JUNE 2022 TMS320x2806x Microcontrollers Submit Document Feedback Copyright © 2022 Texas Instruments Incorporated...
Page 57 Device unsecure User can access Correct password? on-chip secure memory The KEY registers are EALLOW protected. Figure 1-11. Password Match Flow (PMF) SPRUH18I – JANUARY 2011 – REVISED JUNE 2022 TMS320x2806x Microcontrollers Submit Document Feedback Copyright © 2022 Texas Instruments Incorporated...
Page 58 CSM protected memory region. The Boot ROM code does this dummy read for convenience. TMS320x2806x Microcontrollers SPRUH18I – JANUARY 2011 – REVISED JUNE 2022 Submit Document Feedback Copyright © 2022 Texas Instruments Incorporated...
Page 59 *CSMSCR = 0x00AEF; //CSMSCR register //Set FORCESEC bit asm(" EALLOW"); //CSMSCR register is EALLOW protected. *CSMSCR = 0x8000; asm("EDIS"); SPRUH18I – JANUARY 2011 – REVISED JUNE 2022 TMS320x2806x Microcontrollers Submit Document Feedback Copyright © 2022 Texas Instruments Incorporated...
Page 60 6. Complete access to secure memory from both the CPU code and the debugger is granted while the device is unsecured. TMS320x2806x Microcontrollers SPRUH18I – JANUARY 2011 – REVISED JUNE 2022 Submit Document Feedback Copyright © 2022 Texas Instruments Incorporated...
Page 61 Device is unsecure (CSM unlocked). Device is secure (CSM locked). This register is EALLOW protected. Refer to Section 1.5.2 for more information. SPRUH18I – JANUARY 2011 – REVISED JUNE 2022 TMS320x2806x Microcontrollers Submit Document Feedback Copyright © 2022 Texas Instruments Incorporated...
Page 62: Clocking
Figure 1-13. Clock and Reset Domains The PLL, clocking, watchdog, and low-power modes, are controlled by the registers listed in Table 1-14. TMS320x2806x Microcontrollers SPRUH18I – JANUARY 2011 – REVISED JUNE 2022 Submit Document Feedback Copyright © 2022 Texas Instruments Incorporated...
Page 63 HRPWM ENCLK ENCLK ENCLK R/W-0 R/W-0 R/W-0 R/W-0 LEGEND: R/W = Read/Write; R = Read only; -n = value after reset SPRUH18I – JANUARY 2011 – REVISED JUNE 2022 TMS320x2806x Microcontrollers Submit Document Feedback Copyright © 2022 Texas Instruments Incorporated...
Page 64 HRPWM is enabled. If a peripheral block is not used, the clock to that peripheral can be turned off to minimize power consumption. TMS320x2806x Microcontrollers SPRUH18I – JANUARY 2011 – REVISED JUNE 2022 Submit Document Feedback Copyright © 2022 Texas Instruments Incorporated...
Page 65 EPWM4ENCLK ePWM4 clock enable. The ePWM4 module is not clocked. (default) The ePWM4 module is clocked by the system clock (SYSCLKOUT). SPRUH18I – JANUARY 2011 – REVISED JUNE 2022 TMS320x2806x Microcontrollers Submit Document Feedback Copyright © 2022 Texas Instruments Incorporated...
Page 66 If a peripheral block is not used, the clock to that peripheral can be turned off to minimize power consumption. To start the ePWM Time-base clock (TBCLK) within the ePWM modules, the TBCLKSYNC bit in PCLKCR0 must also be set. TMS320x2806x Microcontrollers SPRUH18I – JANUARY 2011 – REVISED JUNE 2022 Submit Document Feedback Copyright © 2022 Texas Instruments Incorporated...
Page 67 Any writes to these bits must always have a value of 0. If a peripheral block is not used, the clock to that peripheral can be turned off to minimize power consumption. SPRUH18I – JANUARY 2011 – REVISED JUNE 2022 TMS320x2806x Microcontrollers Submit Document Feedback Copyright © 2022 Texas Instruments Incorporated...
Page 68 Comparator2 clock enable Comparator2 is not clocked Comparator2 is clocked COMP1ENCLK Comparator1 clock enable Comparator1 is not clocked Comparator1 is clocked TMS320x2806x Microcontrollers SPRUH18I – JANUARY 2011 – REVISED JUNE 2022 Submit Document Feedback Copyright © 2022 Texas Instruments Incorporated...
Page 69 XCLKIN is multiplexed with GPIO19 or GPIO38 pin. The XCLKIN input can be selected as GPIO19 or GPIO38 via the XCLKINSEL bit in XCLK register. The CLKCTL[XCLKINOFF] bit disables this clock input SPRUH18I – JANUARY 2011 – REVISED JUNE 2022 TMS320x2806x Microcontrollers Submit Document Feedback Copyright © 2022 Texas Instruments Incorporated...
Page 70 0 = OSC on (default on reset) CLKCTL[XTALOSCOFF] 1 = Turn OSC off Register loaded from TI OTP-based calibration function. Figure 1-19. Clocking Options TMS320x2806x Microcontrollers SPRUH18I – JANUARY 2011 – REVISED JUNE 2022 Submit Document Feedback Copyright © 2022 Texas Instruments Incorporated...
Page 71 Step 2: Call the function pointed to by Device_cal() as shown in Example 1-1. The ADC clocks must be enabled before making this call. SPRUH18I – JANUARY 2011 – REVISED JUNE 2022 TMS320x2806x Microcontrollers Submit Document Feedback Copyright © 2022 Texas Instruments Incorporated...
Page 72 The XCLKINSEL bit in the XCLK register is reset by XRS input signal. Refer to the device data sheet for the maximum permissible XCLKOUT frequency. TMS320x2806x Microcontrollers SPRUH18I – JANUARY 2011 – REVISED JUNE 2022 Submit Document Feedback Copyright © 2022 Texas Instruments Incorporated...
Page 73 Internal oscillator 2 Off. This bit could be used by the user to turn off the internal oscillator 2 if it is not used. This selection is not affected by the missing clock detect circuit. SPRUH18I – JANUARY 2011 – REVISED JUNE 2022 TMS320x2806x Microcontrollers Submit Document Feedback Copyright © 2022 Texas Instruments Incorporated...
Page 74 This selection is not affected by the missing clock detect circuit. External oscillator selected (default on reset) Internal oscillator 2 selected TMS320x2806x Microcontrollers SPRUH18I – JANUARY 2011 – REVISED JUNE 2022 Submit Document Feedback Copyright © 2022 Texas Instruments Incorporated...
Page 75 Second write → CLKCTL.OSCCLKLSRCSEL=1 and CLKCTL.OSCCLKSRC2SEL=1 The second write should not alter the values of XTALOSCOFF and XCLKINOFF bits. If C2000Ware, supplied by Texas Instruments is used, clock switching can be achieved with the following code snip: SysCtrlRegs.CLKCTL.all = 0x6000; // Set XTALOSCOFF=1 & XCLKINOFF=1 SysCtrlRegs.CLKCTL.all = 0x6003;...
Page 76 PLLLOCKS bit to determine when the PLL has completed locking. Once PLLSTS[PLLLOCKS] = 1, DIVSEL can be changed. Follow the procedure in Figure 1-24 any time you are writing to the PLLCR register. TMS320x2806x Microcontrollers SPRUH18I – JANUARY 2011 – REVISED JUNE 2022 Submit Document Feedback Copyright © 2022 Texas Instruments Incorporated...
Page 77 If required, PLLSTS [DIVSEL] can now be changed. Figure 1-24. PLLCR Change Procedure Flow Chart SPRUH18I – JANUARY 2011 – REVISED JUNE 2022 TMS320x2806x Microcontrollers Submit Document Feedback Copyright © 2022 Texas Instruments Incorporated...
Page 78 The PLL control register (PLLCR) and PLL Status Register (PLLSTS) are reset to their default state by the XRS signal or a watchdog reset only. A reset issued by the debugger or the missing clock detect logic have no effect. TMS320x2806x Microcontrollers SPRUH18I – JANUARY 2011 – REVISED JUNE 2022 Submit Document Feedback Copyright © 2022 Texas Instruments Incorporated...
Page 79 (MCLKSTS), and the CPU will be clocked by the PLL operating at a limp mode frequency. SPRUH18I – JANUARY 2011 – REVISED JUNE 2022 TMS320x2806x Microcontrollers Submit Document Feedback Copyright © 2022 Texas Instruments Incorporated...
Page 80 This register is reset to its default state only by the XRS signal or a watchdog reset. It is not reset by a missing clock or debugger reset. This register is EALLOW protected. See Section 1.5.2 for more information. TMS320x2806x Microcontrollers SPRUH18I – JANUARY 2011 – REVISED JUNE 2022 Submit Document Feedback Copyright © 2022 Texas Instruments Incorporated...
Page 81 0 OSCCLK Cycles (no PLL lock period) PLLLOCKPRD is affected by the XRSn signal only. This register is EALLOW protected. See Section 1.5.2 for more information. SPRUH18I – JANUARY 2011 – REVISED JUNE 2022 TMS320x2806x Microcontrollers Submit Document Feedback Copyright © 2022 Texas Instruments Incorporated...
Page 82 PLL overshoot. The user will then have to write to the DEVICECNF[SYSCLK2DIV2DIS] bit to configure the appropriate divisor ratio. This register is EALLOW protected. See Section 1.5.2 for more information. TMS320x2806x Microcontrollers SPRUH18I – JANUARY 2011 – REVISED JUNE 2022 Submit Document Feedback Copyright © 2022 Texas Instruments Incorporated...
Page 83 Upon reaching zero, the counter stops and the PLL2LOCKS bit is set. PLL2 is not yet locked PLL2 is locked SPRUH18I – JANUARY 2011 – REVISED JUNE 2022 TMS320x2806x Microcontrollers Submit Document Feedback Copyright © 2022 Texas Instruments Incorporated...
Page 84 What happens next is based on which clock source has been chosen for the PLL and the value of NMIRESETSEL. TMS320x2806x Microcontrollers SPRUH18I – JANUARY 2011 – REVISED JUNE 2022 Submit Document Feedback Copyright © 2022 Texas Instruments Incorporated...
Page 85 XCLKOUT OSCCLK Counter /1, /2, XCLK Reg (7 bits) /4, off clear clear SYSCLKOUT Sync Figure 1-34. Clocking and Reset Logic SPRUH18I – JANUARY 2011 – REVISED JUNE 2022 TMS320x2806x Microcontrollers Submit Document Feedback Copyright © 2022 Texas Instruments Incorporated...
Page 86 OSCCLKSRC2 as the source for the PLL is that the clock source is automatically switched to INTOSC1 upon loss of OSCCLKSRC2. TMS320x2806x Microcontrollers SPRUH18I – JANUARY 2011 – REVISED JUNE 2022 Submit Document Feedback Copyright © 2022 Texas Instruments Incorporated...
Page 87 CPU. The device will now run at the PLL limp mode frequency or at one-half or one-fourth of the PLL limp mode frequency depending on the state of the PLLSTS[DIVSEL] bit. SPRUH18I – JANUARY 2011 – REVISED JUNE 2022 TMS320x2806x Microcontrollers Submit Document Feedback Copyright © 2022 Texas Instruments Incorporated...
Page 88 The NMI watchdog module is clocked by SYSCLKOUT. Due to the limp mode function of the PLL, SYSCLKOUT is present even if the source clock for OSCCLK fails. Figure 1-35. Clock Fail Interrupt TMS320x2806x Microcontrollers SPRUH18I – JANUARY 2011 – REVISED JUNE 2022 Submit Document Feedback Copyright © 2022 Texas Instruments Incorporated...
Page 89 Writes of 0 are ignored. Reading the bit will indicate if the flag is enabled or disabled: CLOCKFAIL Interrupt Disabled CLOCKFAIL Interrupt Enabled Reserved Any writes to these bits must always have a value of 0. SPRUH18I – JANUARY 2011 – REVISED JUNE 2022 TMS320x2806x Microcontrollers Submit Document Feedback Copyright © 2022 Texas Instruments Incorporated...
Page 90 If hardware is trying to set a bit to 1 while software is trying to clear a bit to 0 on the same cycle, hardware has priority. You should clear the pending CLOCKFAIL flag first and then clear the NMIINT flag. TMS320x2806x Microcontrollers SPRUH18I – JANUARY 2011 – REVISED JUNE 2022 Submit Document Feedback Copyright © 2022 Texas Instruments Incorporated...
Page 91 The counter is clocked at the SYSCLKOUT rate. Reset value of this counter is zero. SPRUH18I – JANUARY 2011 – REVISED JUNE 2022 TMS320x2806x Microcontrollers Submit Document Feedback Copyright © 2022 Texas Instruments Incorporated...
Page 92 Real-Time Run-Free Mode: When the CPU is in real-time run-free mode, the NMI watchdog counter operates as normal. TMS320x2806x Microcontrollers SPRUH18I – JANUARY 2011 – REVISED JUNE 2022 Submit Document Feedback Copyright © 2022 Texas Instruments Incorporated...
Page 93 On the 28x, the JTAG port can still function even if the clock to the CPU (CLKIN) is turned off. SPRUH18I – JANUARY 2011 – REVISED JUNE 2022 TMS320x2806x Microcontrollers Submit Document Feedback Copyright © 2022 Texas Instruments Incorporated...
Page 94 PLL has locked, it feeds the CLKIN to the CPU at which time the CPU responds to the WAKEINT interrupt if enabled. The low-power modes are controlled by the LPMCR0 register (Figure 1-43). TMS320x2806x Microcontrollers SPRUH18I – JANUARY 2011 – REVISED JUNE 2022 Submit Document Feedback Copyright © 2022 Texas Instruments Incorporated...
Page 95 Wakeup from STANDBY: Set WDINTE bit in LPMCR0 register to 1. When the device wakes up from STANDBY, it will be through the WAKEINT interrupt (Interrupt 1.8 in the PIE). SPRUH18I – JANUARY 2011 – REVISED JUNE 2022 TMS320x2806x Microcontrollers Submit Document Feedback Copyright © 2022 Texas Instruments Incorporated...
Page 96 WDINT signal will be driven low for 512 OSCCLK cycles when an interrupt occurs. Figure 1-44. CPU Watchdog Module TMS320x2806x Microcontrollers SPRUH18I – JANUARY 2011 – REVISED JUNE 2022 Submit Document Feedback Copyright © 2022 Texas Instruments Incorporated...
Page 97 If the watchdog is disabled before WDINT goes inactive, the 512-cycle count will halt and WDINT will remain active. The count will resume when the watchdog is enabled again. SPRUH18I – JANUARY 2011 – REVISED JUNE 2022 TMS320x2806x Microcontrollers Submit Document Feedback Copyright © 2022 Texas Instruments Incorporated...
Page 98 Real-Time Run-Free Mode: When the CPU is in real-time run-free mode, the watchdog operates as normal. TMS320x2806x Microcontrollers SPRUH18I – JANUARY 2011 – REVISED JUNE 2022 Submit Document Feedback Copyright © 2022 Texas Instruments Incorporated...
Page 99 1, and writing a 1 clears this bit (bit becomes 0) and the WD cannot be disabled. Writing a 0 has no effect. This register is EALLOW protected. See Section 1.5.2 for more information. SPRUH18I – JANUARY 2011 – REVISED JUNE 2022 TMS320x2806x Microcontrollers Submit Document Feedback Copyright © 2022 Texas Instruments Incorporated...
Page 100 Reads from WDKEY return the value of the WDCR register. This register is EALLOW protected. See Section 1.5.2 for more information. TMS320x2806x Microcontrollers SPRUH18I – JANUARY 2011 – REVISED JUNE 2022 Submit Document Feedback Copyright © 2022 Texas Instruments Incorporated...
Page 101 XRS input. Hence to distinguish between a watchdog reset and an external device reset, an external reset must be longer in duration then the watchdog pulse. SPRUH18I – JANUARY 2011 – REVISED JUNE 2022 TMS320x2806x Microcontrollers Submit Document Feedback Copyright © 2022 Texas Instruments Incorporated...
Page 102 The timing of the timers is synchronized to SYSCLKOUT of the processor clock. Figure 1-50. CPU-Timer Interrupts Signals and Output Signal TMS320x2806x Microcontrollers SPRUH18I – JANUARY 2011 – REVISED JUNE 2022 Submit Document Feedback Copyright © 2022 Texas Instruments Incorporated...
Page 103 CPU-Timer 2, Control Register Figure 1-55 TIMER2TPR 0x0C16 CPU-Timer 2, Prescale Register Figure 1-56 TIMER2TPRH 0x0C17 CPU-Timer 2, Prescale Register High Figure 1-57 SPRUH18I – JANUARY 2011 – REVISED JUNE 2022 TMS320x2806x Microcontrollers Submit Document Feedback Copyright © 2022 Texas Instruments Incorporated...
Page 104 LEGEND: R/W = Read/Write; R = Read only; -n = value after reset Table 1-49. TIMERxTIMH Register Field Descriptions Bits Field Description 15-0 TIMH See description for TIMERxTIM. TMS320x2806x Microcontrollers SPRUH18I – JANUARY 2011 – REVISED JUNE 2022 Submit Document Feedback Copyright © 2022 Texas Instruments Incorporated...
Page 105 R/W-0 R/W-0 R/W-0 R/W-0 Reserved Reserved R/W-0 R/W-0 LEGEND: R/W = Read/Write; R = Read only; -n = value after reset SPRUH18I – JANUARY 2011 – REVISED JUNE 2022 TMS320x2806x Microcontrollers Submit Document Feedback Copyright © 2022 Texas Instruments Incorporated...
Page 106 To stop the CPU-timer, set TSS to 1. Reserved Any writes to these bits must always have a value of 0. TMS320x2806x Microcontrollers SPRUH18I – JANUARY 2011 – REVISED JUNE 2022 Submit Document Feedback Copyright © 2022 Texas Instruments Incorporated...
Page 107: General-Purpose Input/Output (Gpio)
GPIO module. Note that GPIO functionality is provided on JTAG pins as well. SPRUH18I – JANUARY 2011 – REVISED JUNE 2022 TMS320x2806x Microcontrollers Submit Document Feedback Copyright © 2022 Texas Instruments Incorporated...
Page 108 Peripheral 2 output enable Peripheral 3 output enable GPxDAT latch/read are accessed at the same memory location. Figure 1-58. General GPIO Multiplexing Diagram TMS320x2806x Microcontrollers SPRUH18I – JANUARY 2011 – REVISED JUNE 2022 Submit Document Feedback Copyright © 2022 Texas Instruments Incorporated...
Page 109 The input qualification circuit is not reset when modes are changed (such as changing from output to input mode). Any state will get flushed by the circuit eventually. Figure 1-59. GPIO32, GPIO33 Multiplexing Diagram SPRUH18I – JANUARY 2011 – REVISED JUNE 2022 TMS320x2806x Microcontrollers Submit Document Feedback Copyright © 2022 Texas Instruments Incorporated...
Page 110 TRST XCLKIN GPIO38_in TCK/GPIO38 GPIO38_out C28x Core GPIO37_in TDO/GPIO37 GPIO37_out GPIO36_in TMS/GPIO36 GPIO36_out GPIO35_in TDI/GPIO35 GPIO35_out Figure 1-60. JTAG Port/GPIO Multiplexing TMS320x2806x Microcontrollers SPRUH18I – JANUARY 2011 – REVISED JUNE 2022 Submit Document Feedback Copyright © 2022 Texas Instruments Incorporated...
Page 111 This bit is reset by TRST. The bit is forced to "0" when TRST is "0". When TRST is "1", then JTAGDIS bit can be modified by CPU. Note: Ensure no contention with the debug probe signals when JTAGDIS=1 SPRUH18I – JANUARY 2011 – REVISED JUNE 2022 TMS320x2806x Microcontrollers Submit Document Feedback Copyright © 2022 Texas Instruments Incorporated...
Page 112 The ADC/Comparator path is always enabled, irrespective of the AIOMUX1 value. The AIO section is blocked off when the corresponding AIOMUX1 bit is 1. Figure 1-62. Analog/GPIO Multiplexing TMS320x2806x Microcontrollers SPRUH18I – JANUARY 2011 – REVISED JUNE 2022 Submit Document Feedback Copyright © 2022 Texas Instruments Incorporated...
Page 113 All other GPIO-capable pins have the pullup enabled by default. The AIOx pins do not have internal pull-up resistors. SPRUH18I – JANUARY 2011 – REVISED JUNE 2022 TMS320x2806x Microcontrollers Submit Document Feedback Copyright © 2022 Texas Instruments Incorporated...
Page 114 There is a 2-SYSCLKOUT cycle delay from when a write to configuration registers such as GPxMUXn and GPxQSELn occurs to when the action is valid TMS320x2806x Microcontrollers SPRUH18I – JANUARY 2011 – REVISED JUNE 2022 Submit Document Feedback Copyright © 2022 Texas Instruments Incorporated...
Page 115 (1) on the pin. During this lag, the second instruction will read the old value of GPIO1 (0) and write it back along with the new value of GPIO2 (1). Therefore, GPIO1 pin stays low. SPRUH18I – JANUARY 2011 – REVISED JUNE 2022 TMS320x2806x Microcontrollers Submit Document Feedback Copyright © 2022 Texas Instruments Incorporated...
Page 116 SYSCLKOUT period of delay in order for the input to the device to be changed. No further qualification is performed on the signal. TMS320x2806x Microcontrollers SPRUH18I – JANUARY 2011 – REVISED JUNE 2022 Submit Document Feedback Copyright © 2022 Texas Instruments Incorporated...
Page 117 If GPxCTRL[QUALPRDn] = 0 SYSCLKOUT If GPxCTRL[QUALPRDn] ≠ 0 × 1 ÷ (2 × GPxCTRL[QUALPRDn]) SYSCLKOUT Where f is the frequency of SYSCLKOUT SYSCLKOUT SPRUH18I – JANUARY 2011 – REVISED JUNE 2022 TMS320x2806x Microcontrollers Submit Document Feedback Copyright © 2022 Texas Instruments Incorporated...
Page 118 If GPxCTRL[QUALPRDn] ≠ 0 5 × 2 × GPxCTRL[QUALPRDn] × T SYSCLKOUT Where T is the period in time of SYSCLKOUT SYSCLKOUT TMS320x2806x Microcontrollers SPRUH18I – JANUARY 2011 – REVISED JUNE 2022 Submit Document Feedback Copyright © 2022 Texas Instruments Incorporated...
Page 119 (5 x QUALPRD x 2) SYSCLKOUT cycles. That would ensure 5 sampling periods for detection to occur. Since external signals are driven asynchronously, an 13-SYSCLKOUT-wide pulse ensures reliable recognition. Figure 1-64. Input Qualifier Clock Cycles SPRUH18I – JANUARY 2011 – REVISED JUNE 2022 TMS320x2806x Microcontrollers Submit Document Feedback Copyright © 2022 Texas Instruments Incorporated...
Page 120 SPISIMOB were assigned to both GPIO12 and GPIO24, the input to the SPI peripheral would default to a high state as shown in Table 1-63 and the input would not be connected to GPIO12 or GPIO24. TMS320x2806x Microcontrollers SPRUH18I – JANUARY 2011 – REVISED JUNE 2022 Submit Document Feedback Copyright © 2022 Texas Instruments Incorporated...
Page 121 This value will be assigned to the peripheral input if more then one pin has been assigned to the peripheral function in the GPxMUX1/2 registers or if no pin has been assigned. SPRUH18I – JANUARY 2011 – REVISED JUNE 2022 TMS320x2806x Microcontrollers Submit Document Feedback Copyright © 2022 Texas Instruments Incorporated...
Page 122 This selection is a reserved configuration for future expansion. I = Input, O = Output, OD = Open Drain eQEP2 is not available on the 80-pin PN/PFP package. TMS320x2806x Microcontrollers SPRUH18I – JANUARY 2011 – REVISED JUNE 2022 Submit Document Feedback Copyright © 2022 Texas Instruments Incorporated...
Page 123 This selection is a reserved configuration for future expansion. I = Input, O = Output, OD = Open Drain This pin is not available in the 80-pin PN/PFP package. SPRUH18I – JANUARY 2011 – REVISED JUNE 2022 TMS320x2806x Microcontrollers Submit Document Feedback Copyright © 2022 Texas Instruments Incorporated...
Page 124 TZ3 - Trip zone 3 (I) SCITXDB (O) SPICLKB (IO) - SPI-B clock This option is reserved on devices that do not have an SPI-B port. TMS320x2806x Microcontrollers SPRUH18I – JANUARY 2011 – REVISED JUNE 2022 Submit Document Feedback Copyright © 2022 Texas Instruments Incorporated...
Page 125 GPIO5 - General purpose I/O 5 (default) (I/O) EPWM3B - ePWM3 output B SPISIMOA (I/O) - SPI-A Slave input/Master output ECAP1 - eCAP1 (I/O) SPRUH18I – JANUARY 2011 – REVISED JUNE 2022 TMS320x2806x Microcontrollers Submit Document Feedback Copyright © 2022 Texas Instruments Incorporated...
Page 126 Configure the GPIO0 pin as: GPIO0 - General purpose I/O 0 (default) (I/O) EPWM1A - ePWM1 output A (O) Reserved Reserved TMS320x2806x Microcontrollers SPRUH18I – JANUARY 2011 – REVISED JUNE 2022 Submit Document Feedback Copyright © 2022 Texas Instruments Incorporated...
Page 127 Configure the GPIO26 pin as: GPIO26 - General purpose I/O 26 (default) (I/O) ECAP3 (I/O) EQEP2I (I/O) SPICLKB (I/O) - SPI-B clock SPRUH18I – JANUARY 2011 – REVISED JUNE 2022 TMS320x2806x Microcontrollers Submit Document Feedback Copyright © 2022 Texas Instruments Incorporated...
Page 128 GPIO17 - General purpose I/O 17 (default) (I/O) SPISOMIA - SPI-A Slave output/Master input (I/O) Reserved TZ3 - Trip zone 3 (I) TMS320x2806x Microcontrollers SPRUH18I – JANUARY 2011 – REVISED JUNE 2022 Submit Document Feedback Copyright © 2022 Texas Instruments Incorporated...
Page 129 GPIO16 - General purpose I/O 16 (default) (I/O) SPISIMOA - SPI-A slave-in, master-out (I/O), Reserved TZ2 - Trip zone 2 (I) SPRUH18I – JANUARY 2011 – REVISED JUNE 2022 TMS320x2806x Microcontrollers Submit Document Feedback Copyright © 2022 Texas Instruments Incorporated...
Page 130 SCITXDB (O) Reserved 15:14 GPIO39 Configure this pin as: GPIO39 - general purpose I/O 39 (default) Reserved 10 or 11 Reserved TMS320x2806x Microcontrollers SPRUH18I – JANUARY 2011 – REVISED JUNE 2022 Submit Document Feedback Copyright © 2022 Texas Instruments Incorporated...
Page 131 C data open drain bidirectional port (I/O) EPWMSYNCI - External ePWM sync pulse input (I) ADCSOCAO - ADC start-of-conversion A (O) SPRUH18I – JANUARY 2011 – REVISED JUNE 2022 TMS320x2806x Microcontrollers Submit Document Feedback Copyright © 2022 Texas Instruments Incorporated...
Page 132 EQEP2A (I) HRCAP1 (I) 11:10 GPIO53 Configure this pin as: GPIO53 - general purpose I/O 53 (default). EQEP1I (I/O) MFSXA (I/O) Reserved TMS320x2806x Microcontrollers SPRUH18I – JANUARY 2011 – REVISED JUNE 2022 Submit Document Feedback Copyright © 2022 Texas Instruments Incorporated...
Page 133 GPIO50 - general purpose I/O 50 (default) EQEP1A (I) MDXA (O) TZ1 (I) Reserved Any writes to these bits must always have a value of 0. SPRUH18I – JANUARY 2011 – REVISED JUNE 2022 TMS320x2806x Microcontrollers Submit Document Feedback Copyright © 2022 Texas Instruments Incorporated...
Page 134 AIO2 enabled 10 or 11 AIO2 disabled (default) Reserved Any writes to these bits must always have a value of 0. TMS320x2806x Microcontrollers SPRUH18I – JANUARY 2011 – REVISED JUNE 2022 Submit Document Feedback Copyright © 2022 Texas Instruments Incorporated...
Page 135 SYSCLKOUT ..0xFF Sampling Period = 510 × T SYSCLKOUT indicates the period of SYSCLKOUT. SYSCLKOUT SPRUH18I – JANUARY 2011 – REVISED JUNE 2022 TMS320x2806x Microcontrollers Submit Document Feedback Copyright © 2022 Texas Instruments Incorporated...
Page 136 SYSCLKOUT ..0xFF Sampling Period = 510 × T SYSCLKOUT indicates the period of SYSCLKOUT. SYSCLKOUT TMS320x2806x Microcontrollers SPRUH18I – JANUARY 2011 – REVISED JUNE 2022 Submit Document Feedback Copyright © 2022 Texas Instruments Incorporated...
Page 137 USB0DP and USB0DM pins are controlled by GPIO Mux register settings. USBPHY is powered down. USB0DP and USB0DM pins configured as USB function. GPIO function is disabled. SPRUH18I – JANUARY 2011 – REVISED JUNE 2022 TMS320x2806x Microcontrollers Submit Document Feedback Copyright © 2022 Texas Instruments Incorporated...
Page 138 If the pin is configured as a GPIO input, then this option is the same as 0,0 or synchronize to SYSCLKOUT. TMS320x2806x Microcontrollers SPRUH18I – JANUARY 2011 – REVISED JUNE 2022 Submit Document Feedback Copyright © 2022 Texas Instruments Incorporated...
Page 139 If the pin is configured as a GPIO input, then this option is the same as 0,0 or synchronize to SYSCLKOUT. SPRUH18I – JANUARY 2011 – REVISED JUNE 2022 TMS320x2806x Microcontrollers Submit Document Feedback Copyright © 2022 Texas Instruments Incorporated...
Page 140 If the pin is configured as a GPIO input, then this option is the same as 0,0 or synchronize to SYSCLKOUT. TMS320x2806x Microcontrollers SPRUH18I – JANUARY 2011 – REVISED JUNE 2022 Submit Document Feedback Copyright © 2022 Texas Instruments Incorporated...
Page 141 If the pin is configured as a GPIO input, then this option is the same as 0,0 or synchronize to SYSCLKOUT. SPRUH18I – JANUARY 2011 – REVISED JUNE 2022 TMS320x2806x Microcontrollers Submit Document Feedback Copyright © 2022 Texas Instruments Incorporated...
Page 142 The value currently in the GPADAT output latch is driven on the pin. To initialize the GPADAT latch prior to changing the pin from an input to an output, use the GPASET, GPACLEAR, and GPATOGGLE registers. TMS320x2806x Microcontrollers SPRUH18I – JANUARY 2011 – REVISED JUNE 2022 Submit Document Feedback Copyright © 2022 Texas Instruments Incorporated...
Page 143 Configures the GPIO pin as an input. (default) Configures the GPIO pin as an output SPRUH18I – JANUARY 2011 – REVISED JUNE 2022 TMS320x2806x Microcontrollers Submit Document Feedback Copyright © 2022 Texas Instruments Incorporated...
Page 144 Configures the AIO pin as an input. (default) Configures the AIO pin as an output TMS320x2806x Microcontrollers SPRUH18I – JANUARY 2011 – REVISED JUNE 2022 Submit Document Feedback Copyright © 2022 Texas Instruments Incorporated...
Page 145 Enable the internal pullup on the specified pin. (default for GPIO12-GPIO31) Disable the internal pullup on the specified pin. (default for GPIO0-GPIO11) SPRUH18I – JANUARY 2011 – REVISED JUNE 2022 TMS320x2806x Microcontrollers Submit Document Feedback Copyright © 2022 Texas Instruments Incorporated...
Page 146 Enable the internal pullup on the specified pin. (default for GPIO39-GPIO32) Disable the internal pullup on the specified pin TMS320x2806x Microcontrollers SPRUH18I – JANUARY 2011 – REVISED JUNE 2022 Submit Document Feedback Copyright © 2022 Texas Instruments Incorporated...
Page 147 Writing a 1will force an output of 1if the pin is configured as a GPIO output in the appropriate GPAMUX1/2 and GPADIR registers; otherwise, the value is latched but not used to drive the pin. SPRUH18I – JANUARY 2011 – REVISED JUNE 2022 TMS320x2806x Microcontrollers Submit Document Feedback Copyright © 2022 Texas Instruments Incorporated...
Page 148 Writing a 1 will force an output of 1 if the pin is configured as a GPIO output in the GPBMUX1 and GPBDIR registers; otherwise, the value is latched but not used to drive the pin. TMS320x2806x Microcontrollers SPRUH18I – JANUARY 2011 – REVISED JUNE 2022 Submit Document Feedback Copyright © 2022 Texas Instruments Incorporated...
Page 149 Writing a 1will force an output of 1if the pin is configured as a AIO output in the appropriate registers; otherwise, the value is latched but not used to drive the pin. SPRUH18I – JANUARY 2011 – REVISED JUNE 2022 TMS320x2806x Microcontrollers Submit Document Feedback Copyright © 2022 Texas Instruments Incorporated...
Page 150 If the pin is not configured as a GPIO output then the latch is cleared but the pin is not driven. TMS320x2806x Microcontrollers SPRUH18I – JANUARY 2011 – REVISED JUNE 2022 Submit Document Feedback Copyright © 2022 Texas Instruments Incorporated...
Page 151 GPIO output then it will be driven in the opposite direction of its current state. If the pin is not configured as a GPIO output then the latch is toggled but the pin is not driven. SPRUH18I – JANUARY 2011 – REVISED JUNE 2022 TMS320x2806x Microcontrollers Submit Document Feedback Copyright © 2022 Texas Instruments Incorporated...
Page 152 If the pin is not configured as a GPIO output then the latch is set but the pin is not driven. TMS320x2806x Microcontrollers SPRUH18I – JANUARY 2011 – REVISED JUNE 2022 Submit Document Feedback Copyright © 2022 Texas Instruments Incorporated...
Page 153 GPIO output then it will be driven in the opposite direction of its current state. If the pin is not configured as a GPIO output then the latch is cleared but the pin is not driven. SPRUH18I – JANUARY 2011 – REVISED JUNE 2022 TMS320x2806x Microcontrollers Submit Document Feedback Copyright © 2022 Texas Instruments Incorporated...
Page 154 AIO output then it will be driven in the opposite direction of its current state. If the pin is not configured as a AIO output then the latch is cleared but the pin is not driven. TMS320x2806x Microcontrollers SPRUH18I – JANUARY 2011 – REVISED JUNE 2022 Submit Document Feedback Copyright © 2022 Texas Instruments Incorporated...
Page 155 Table 1-97. XINT1/XINT2/XINT3 Interrupt Select and Configuration Registers Interrupt Interrupt Select Register Configuration Register XINT1 GPIOXINT1SEL XINT1CR XINT2 GPIOXINT2SEL XINT2CR XINT3 GPIOXINT3SEL XINT3CR SPRUH18I – JANUARY 2011 – REVISED JUNE 2022 TMS320x2806x Microcontrollers Submit Document Feedback Copyright © 2022 Texas Instruments Incorporated...
Page 156 If the respective bit is set to 1, the signal on the corresponding pin is able to wake the device from both HALT and STANDBY low power modes. TMS320x2806x Microcontrollers SPRUH18I – JANUARY 2011 – REVISED JUNE 2022 Submit Document Feedback Copyright © 2022 Texas Instruments Incorporated...
Page 157: Peripheral Frames
The Flash Registers are also protected by the Code Security Module (CSM). SPRUH18I – JANUARY 2011 – REVISED JUNE 2022 TMS320x2806x Microcontrollers Submit Document Feedback Copyright © 2022 Texas Instruments Incorporated...
Page 158 NAME ADDRESS RANGE SIZE (×16) EALLOW PROTECTED USB0 Registers 0x00 4000 – 0x4FFF 4096 McBSP-A Registers 0x00 5000 – 0x00 503F TMS320x2806x Microcontrollers SPRUH18I – JANUARY 2011 – REVISED JUNE 2022 Submit Document Feedback Copyright © 2022 Texas Instruments Incorporated...
Page 159 Flash Standby To Active Wait State Register FBANKWAIT 0x0A86 Flash Read Access Wait State Register FOTPWAIT 0x0A87 OTP Read Access Wait State Register SPRUH18I – JANUARY 2011 – REVISED JUNE 2022 TMS320x2806x Microcontrollers Submit Document Feedback Copyright © 2022 Texas Instruments Incorporated...
Page 160 PLL2STS 0x00 7034 PLL2 Lock Status Register SYSCLK2CNTR 0x00 7036 SYSCLK2 Clock Counter Register EPWMCFG 0x00 703A ePWM DMA/CLA Configuration Register TMS320x2806x Microcontrollers SPRUH18I – JANUARY 2011 – REVISED JUNE 2022 Submit Document Feedback Copyright © 2022 Texas Instruments Incorporated...
Page 161 Trip Zone Enable Interrupt Register (TZEINT) • Trip Zone Clear Register (TZCLR) • Trip Zone Force Register (TZFRC) • HRPWM Configuration Register (HRCNFG) SPRUH18I – JANUARY 2011 – REVISED JUNE 2022 TMS320x2806x Microcontrollers Submit Document Feedback Copyright © 2022 Texas Instruments Incorporated...
Page 162 0x6912 0x6914 0x6915 0x6917 0x6918 0x6920 ePWM6 0x6952 0x6954 0x6955 0x6957 0x6958 0x6960 ePWM7 0x6992 0x6994 0x6995 0x6997 0x6998 0x69A0 TMS320x2806x Microcontrollers SPRUH18I – JANUARY 2011 – REVISED JUNE 2022 Submit Document Feedback Copyright © 2022 Texas Instruments Incorporated...
Page 163 VMAP Configure Status. This indicates the status of VMAP. Reserved Any writes to these bits must always have a value of 0. SPRUH18I – JANUARY 2011 – REVISED JUNE 2022 TMS320x2806x Microcontrollers Submit Document Feedback Copyright © 2022 Texas Instruments Incorporated...
Page 164 0x6E TMS320F28064UPZP/PZ 0x6F TMS320F28064PFP/PN 0x6C TMS320F28064UPFP/PN 0x6D TMS320F28063PZP/PZ 0x6A TMS320F28063UPZP/PZ 0x6B TMS320F28063PFP/PN 0x68 TMS320F28063UPFP/PN 0x69 TMS320F28062PZP/PZ 0x66 TMS320F28062UPZP/PZ 0x67 TMS320F28062PFP/PN 0x65 TMS320x2806x Microcontrollers SPRUH18I – JANUARY 2011 – REVISED JUNE 2022 Submit Document Feedback Copyright © 2022 Texas Instruments Incorporated...
Page 165 0x0001 Silicon Revision A - TMS The reset value depends on the silicon revision as described in the register field description. SPRUH18I – JANUARY 2011 – REVISED JUNE 2022 TMS320x2806x Microcontrollers Submit Document Feedback Copyright © 2022 Texas Instruments Incorporated...
Page 166 If block protection is enabled, then the read is stalled until the write occurs as shown: @REG1,AL ---------+ TBIT @REG2,#BIT_X ---------|-----+ +-----|---> Write +---> Read TMS320x2806x Microcontrollers SPRUH18I – JANUARY 2011 – REVISED JUNE 2022 Submit Document Feedback Copyright © 2022 Texas Instruments Incorporated...
Page 167: Peripheral Interrupt Expansion (Pie)
External INTx.6 Interrupts INTx.7 INTx.8 PIEACKx (Enable) (Flag) (Enable/Flag) PIEIERx(8:1) PIEIFRx(8:1) Figure 1-93. Overview: Multiplexing of Interrupts Using the PIE Block SPRUH18I – JANUARY 2011 – REVISED JUNE 2022 TMS320x2806x Microcontrollers Submit Document Feedback Copyright © 2022 Texas Instruments Incorporated...
Page 168 CPU interrupt enable (IER) register or the debug interrupt enable register (DBGIER) and the global interrupt mask (INTM) bit. TMS320x2806x Microcontrollers SPRUH18I – JANUARY 2011 – REVISED JUNE 2022 Submit Document Feedback Copyright © 2022 Texas Instruments Incorporated...
Page 169 INTM = 0 and bit in IER is 1 DSP in real-time mode and halted Bit in IER is 1 and DBGIER is 1 SPRUH18I – JANUARY 2011 – REVISED JUNE 2022 TMS320x2806x Microcontrollers Submit Document Feedback Copyright © 2022 Texas Instruments Incorporated...
Page 170 1-118. After a reset the PIE vector table is always disabled. Figure 1-95 illustrates the process by which the vector table mapping is selected. TMS320x2806x Microcontrollers SPRUH18I – JANUARY 2011 – REVISED JUNE 2022 Submit Document Feedback Copyright © 2022 Texas Instruments Incorporated...
Page 171 24x/240xA Source-Compatible C27x Object-Compatible (Default at reset) The reset vector is always fetched from the boot ROM. Figure 1-95. Reset Flow Diagram SPRUH18I – JANUARY 2011 – REVISED JUNE 2022 TMS320x2806x Microcontrollers Submit Document Feedback Copyright © 2022 Texas Instruments Incorporated...
Page 172 System Control NMIRS (See the NMI Watchdog section.) (See the System Control section.) Figure 1-96. PIE Interrupt Sources and External Interrupts XINT1/XINT2/XINT3 TMS320x2806x Microcontrollers SPRUH18I – JANUARY 2011 – REVISED JUNE 2022 Submit Document Feedback Copyright © 2022 Texas Instruments Incorporated...
Page 173 If the PIEIER registers are used to enable and then later disable an interrupt then the procedure described in Section 1.6.3.2 must be followed. SPRUH18I – JANUARY 2011 – REVISED JUNE 2022 TMS320x2806x Microcontrollers Submit Document Feedback Copyright © 2022 Texas Instruments Incorporated...
Page 174 11. Clear the IFR bit for given peripheral group (this is safe operation on CPU IFR register). 12. Clear the PIEACK bit for the PIE group. 13. Enable global interrupts. TMS320x2806x Microcontrollers SPRUH18I – JANUARY 2011 – REVISED JUNE 2022 Submit Document Feedback Copyright © 2022 Texas Instruments Incorporated...
Page 175 PIEIFRx is fetched and used as the branch address. In this manner if an even higher priority enabled interrupt was flagged after Step 7, it will be serviced first. SPRUH18I – JANUARY 2011 – REVISED JUNE 2022 TMS320x2806x Microcontrollers Submit Document Feedback Copyright © 2022 Texas Instruments Incorporated...
Page 176 1-119. Each row in the table shows the 8 interrupts multiplexed into a particular CPU interrupt. The entire PIE vector table, including both MUXed and non-MUXed interrupts, is shown in Table 1-120. TMS320x2806x Microcontrollers SPRUH18I – JANUARY 2011 – REVISED JUNE 2022 Submit Document Feedback Copyright © 2022 Texas Instruments Incorporated...
Page 177 XINT3 (CLA, FPU32) (CLA, FPU32) – – – – – Ext. Int. 3 0xDFE 0xDFC 0xDFA 0xDF8 0xDF6 0xDF4 0xDF2 0xDF0 SPRUH18I – JANUARY 2011 – REVISED JUNE 2022 TMS320x2806x Microcontrollers Submit Document Feedback Copyright © 2022 Texas Instruments Incorporated...
Page 178 0x0000 0D48 XINT2 INT1.6 0x0000 0D4A ADCINT9 (ADC) INT1.7 0x0000 0D4C TINT0 (CPU- Timer0) INT1.8 0x0000 0D4E WAKEINT (LPM/WD) 8 (lowest) TMS320x2806x Microcontrollers SPRUH18I – JANUARY 2011 – REVISED JUNE 2022 Submit Document Feedback Copyright © 2022 Texas Instruments Incorporated...
Page 179 (SPI-B) INT6.5 0x0000 0D98 MRINTA (McBSP-A) INT6.6 0x0000 0D9A MXINTA (McBSP-A) INT6.7 0x0000 0D9C Reserved INT6.8 0x0000 0D9E Reserved 8 (lowest) SPRUH18I – JANUARY 2011 – REVISED JUNE 2022 TMS320x2806x Microcontrollers Submit Document Feedback Copyright © 2022 Texas Instruments Incorporated...
Page 180 0x0000 0DE8 CLA1_INT5 (CLA) INT11.6 0x0000 0DEA CLA1_INT6 (CLA) INT11.7 0x0000 0DEC CLA1_INT7 (CLA) INT11.8 0x0000 0DEE CLA1_INT8 (CLA) 8 (lowest) TMS320x2806x Microcontrollers SPRUH18I – JANUARY 2011 – REVISED JUNE 2022 Submit Document Feedback Copyright © 2022 Texas Instruments Incorporated...
Page 181 PIE, INT11 Group Flag Register PIEIER12 0x0000 - 0CF8 PIE, INT12 Group Enable Register PIEIFR12 0x0000 - 0CF9 PIE, INT12 Group Flag Register SPRUH18I – JANUARY 2011 – REVISED JUNE 2022 TMS320x2806x Microcontrollers Submit Document Feedback Copyright © 2022 Texas Instruments Incorporated...
Page 182 = PIEACK bit 0 - PIEACK bit 11. Bit 0 refers to CPU INT1 up to Bit 11, which refers to CPU INT12 TMS320x2806x Microcontrollers SPRUH18I – JANUARY 2011 – REVISED JUNE 2022 Submit Document Feedback Copyright © 2022 Texas Instruments Incorporated...
Page 183 The PIEIFR register bit is cleared during the interrupt vector fetch portion of the interrupt processing. INTx.5 INTx.4 Hardware has priority over CPU accesses to the PIEIFR registers. INTx.3 INTx.2 INTx.1 SPRUH18I – JANUARY 2011 – REVISED JUNE 2022 TMS320x2806x Microcontrollers Submit Document Feedback Copyright © 2022 Texas Instruments Incorporated...
Page 184 = 1 to 12. INTx means CPU INT1 to INT12 INTx.6 INTx.5 INTx.4 INTx.3 INTx.2 INTx.1 TMS320x2806x Microcontrollers SPRUH18I – JANUARY 2011 – REVISED JUNE 2022 Submit Document Feedback Copyright © 2022 Texas Instruments Incorporated...
Page 185 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 LEGEND: R/W = Read/Write; R = Read only; -n = value after reset SPRUH18I – JANUARY 2011 – REVISED JUNE 2022 TMS320x2806x Microcontrollers Submit Document Feedback Copyright © 2022 Texas Instruments Incorporated...
Page 186 At least one INT5 interrupt is pending. Write a 0 to this bit to clear it to 0 and clear the interrupt request TMS320x2806x Microcontrollers SPRUH18I – JANUARY 2011 – REVISED JUNE 2022 Submit Document Feedback Copyright © 2022 Texas Instruments Incorporated...
Page 187 At least one INT1 interrupt is pending. Write a 0 to this bit to clear it to 0 and clear the interrupt request SPRUH18I – JANUARY 2011 – REVISED JUNE 2022 TMS320x2806x Microcontrollers Submit Document Feedback Copyright © 2022 Texas Instruments Incorporated...
Page 188 Level INT13 is enabled INT12 Interrupt 12 enable. INT12 enables or disables CPU interrupt level INT12. Level INT12 is disabled Level INT12 is enabled TMS320x2806x Microcontrollers SPRUH18I – JANUARY 2011 – REVISED JUNE 2022 Submit Document Feedback Copyright © 2022 Texas Instruments Incorporated...
Page 189 Level INT2 is enabled INT1 Interrupt 1 enable.INT1 enables or disables CPU interrupt level INT1. Level INT1 is disabled Level INT1 is enabled SPRUH18I – JANUARY 2011 – REVISED JUNE 2022 TMS320x2806x Microcontrollers Submit Document Feedback Copyright © 2022 Texas Instruments Incorporated...
Page 190 Level INT11 is enabled INT10 Interrupt 10 enable. INT10 enables or disables CPU interrupt level INT10. Level INT10 is disabled Level INT10 is enabled TMS320x2806x Microcontrollers SPRUH18I – JANUARY 2011 – REVISED JUNE 2022 Submit Document Feedback Copyright © 2022 Texas Instruments Incorporated...
Page 191 Level INT2 is enabled INT1 Interrupt 1 enable.INT1 enables or disables CPU interrupt level INT1. Level INT1 is disabled Level INT1 is enabled SPRUH18I – JANUARY 2011 – REVISED JUNE 2022 TMS320x2806x Microcontrollers Submit Document Feedback Copyright © 2022 Texas Instruments Incorporated...
Page 192 XINT3CTR are identical except for the interrupt number; therefore, Figure 1-106 Table 1-131 represent registers for the external interrupts as XINTnCTR, where n = the interrupt number. TMS320x2806x Microcontrollers SPRUH18I – JANUARY 2011 – REVISED JUNE 2022 Submit Document Feedback Copyright © 2022 Texas Instruments Incorporated...
Page 193: Vreg/Bor/Por
To enable this option, the VREGENZ pin must be pulled high. Refer to the device datasheet for the acceptable range of voltage that must be supplied to the V pins. SPRUH18I – JANUARY 2011 – REVISED JUNE 2022 TMS320x2806x Microcontrollers Submit Document Feedback Copyright © 2022 Texas Instruments Incorporated...
Page 194 Bits Field Value Description 15-1 Reserved Reserved BORENZ BOR enable active low bit. BOR functions are enabled. BOR functions are disabled. TMS320x2806x Microcontrollers SPRUH18I – JANUARY 2011 – REVISED JUNE 2022 Submit Document Feedback Copyright © 2022 Texas Instruments Incorporated...
Page 195 C2000ware in C2000Ware. 2.1 Boot ROM Memory Map............................2.2 Bootloader Features..............................202 2.3 Building the Boot Table............................236 2.4 Bootloader Code Overview............................240 SPRUH18I – JANUARY 2011 – REVISED JUNE 2022 TMS320x2806x Microcontrollers Submit Document Feedback Copyright © 2022 Texas Instruments Incorporated...
Page 196: Boot Rom Memory Map
ROM Version ROM Checksum 0x3F FFC0 Reset Vector CPU Vector Table 0x3F FFFF Figure 2-1. F2806x Memory Map of On-Chip ROM TMS320x2806x Microcontrollers SPRUH18I – JANUARY 2011 – REVISED JUNE 2022 Submit Document Feedback Copyright © 2022 Texas Instruments Incorporated...
Page 197 ROM Version ROM Checksum 0x3F FFC0 Reset Vector CPU Vector Table 0x3F FFFF Figure 2-2. F2806xM/2806xF Memory Map of On-Chip ROM SPRUH18I – JANUARY 2011 – REVISED JUNE 2022 TMS320x2806x Microcontrollers Submit Document Feedback Copyright © 2022 Texas Instruments Incorporated...
Page 198 Approximately 4K of the boot ROM is reserved for floating-point and IQ math tables. These tables are provided to help improve performance and save SARAM space. The floating-point math tables included in the boot ROM are used by the Texas Instruments™ C28x FPU Fast RTS Library.
Page 199 • Rounding and Saturation Table, IQ Math Table – Table size: 360 words SPRUH18I – JANUARY 2011 – REVISED JUNE 2022 TMS320x2806x Microcontrollers Submit Document Feedback Copyright © 2022 Texas Instruments Incorporated...
Page 200 The ENPIE bit is located in the PIECTRL register. The default state of this bit at reset is 0, which disables the Peripheral Interrupt Expansion block (PIE). Figure 2-3. Vector Table Map TMS320x2806x Microcontrollers SPRUH18I – JANUARY 2011 – REVISED JUNE 2022 Submit Document Feedback Copyright © 2022 Texas Instruments Incorporated...
Page 201 0x00 007A INT14 0x3F FFDC 0x00 005C USER11 0x3F FFFC 0x00 007C DLOGINT 0x3F FFDE 0x00 005E USER12 0x3F FFFE 0x00 007E SPRUH18I – JANUARY 2011 – REVISED JUNE 2022 TMS320x2806x Microcontrollers Submit Document Feedback Copyright © 2022 Texas Instruments Incorporated...
Page 202: Bootloader Features
2.2.11. If, instead, you choose to boot directly to Flash, OTP, or SARAM, the entry address is predefined for each of these memory blocks. TMS320x2806x Microcontrollers SPRUH18I – JANUARY 2011 – REVISED JUNE 2022 Submit Document Feedback Copyright © 2022 Texas Instruments Incorporated...
Page 203 In the case of an incorrect key value passed to the loader, the watchdog will be enabled and the device will boot to flash. SPRUH18I – JANUARY 2011 – REVISED JUNE 2022 TMS320x2806x Microcontrollers Submit Document Feedback Copyright © 2022 Texas Instruments Incorporated...
Page 204 If code or data is bootloaded into the address range address range 0x0002-0x004E there is no error checking to prevent it from corrupting the boot ROM stack. TMS320x2806x Microcontrollers SPRUH18I – JANUARY 2011 – REVISED JUNE 2022 Submit Document Feedback Copyright © 2022 Texas Instruments Incorporated...
Page 205 Running the embedded code from "main" • Resetting the MCU These operations and more are covered in the Serial Flash Programming of C2000™ Microcontrollers. SPRUH18I – JANUARY 2011 – REVISED JUNE 2022 TMS320x2806x Microcontrollers Submit Document Feedback Copyright © 2022 Texas Instruments Incorporated...
Page 206 Boot Mode Call ExitBoot Begin execution at EntryPoint Figure 2-6. Boot ROM Function Overview TMS320x2806x Microcontrollers SPRUH18I – JANUARY 2011 – REVISED JUNE 2022 Submit Document Feedback Copyright © 2022 Texas Instruments Incorporated...
Page 207 Connect the debugger. TRST will go high. • Perform a debugger reset and run. The boot loader will use the EMU_BMODE and boot to SCI. SPRUH18I – JANUARY 2011 – REVISED JUNE 2022 TMS320x2806x Microcontrollers Submit Document Feedback Copyright © 2022 Texas Instruments Incorporated...
Page 208 The last six words of user OTP region (0x3D7BFA to 0x3D7BFF) are reserved for the GetMode function usage. TMS320x2806x Microcontrollers SPRUH18I – JANUARY 2011 – REVISED JUNE 2022 Submit Document Feedback Copyright © 2022 Texas Instruments Incorporated...
Page 209 I2C_BOOT and the boot mode pins configured for the Get Mode boot option. I2C boot is also available as an emulation boot option. SPRUH18I – JANUARY 2011 – REVISED JUNE 2022 TMS320x2806x Microcontrollers Submit Document Feedback Copyright © 2022 Texas Instruments Incorporated...
Page 210 Get Mode indicated the boot mode was derived from the values programmed in the OTP_KEY and OTP_BMODE locations. x = don't care. TMS320x2806x Microcontrollers SPRUH18I – JANUARY 2011 – REVISED JUNE 2022 Submit Document Feedback Copyright © 2022 Texas Instruments Incorporated...
Page 211 //that begins at the address shown # define Device_cal (void(*)(void))0x3D7C80 ..EALLOW; SysCtrlRegs.PCLKCR0.bit.ADCENCLK = 1; (*Device_cal)(); SysCtrlRegs.PCLKCR0.bit.ADCENCLK = 0; EDIS; SPRUH18I – JANUARY 2011 – REVISED JUNE 2022 TMS320x2806x Microcontrollers Submit Document Feedback Copyright © 2022 Texas Instruments Incorporated...
Page 212 Execution will then continue at the entry point address as determined by the input data stream contents. TMS320x2806x Microcontrollers SPRUH18I – JANUARY 2011 – REVISED JUNE 2022 Submit Document Feedback Copyright © 2022 Texas Instruments Incorporated...
Page 213 Last word of the last block of the source being loaded Block size of 0000h - indicates end of the source program SPRUH18I – JANUARY 2011 – REVISED JUNE 2022 TMS320x2806x Microcontrollers Submit Document Feedback Copyright © 2022 Texas Instruments Incorporated...
Page 214 For 32-bit values, such as a destination address, the most significant word (MSW) is loaded first, followed by the least significant word (LSW). The bootloaders take this into account when loading an 8-bit data stream. TMS320x2806x Microcontrollers SPRUH18I – JANUARY 2011 – REVISED JUNE 2022 Submit Document Feedback Copyright © 2022 Texas Instruments Incorporated...
Page 215 LSB: Last word of the last block MSB: Last word of the last block n+1 LSB: 00h MSB: 00h - indicates the end of the source SPRUH18I – JANUARY 2011 – REVISED JUNE 2022 TMS320x2806x Microcontrollers Submit Document Feedback Copyright © 2022 Texas Instruments Incorporated...
Page 216 Location Value 0x3F9010 0x0001 0x3F9011 0x0002 0x3F9012 0x0003 0x3F9013 0x0004 0x3F9014 0x0005 0x3F8000 0x7700 0x3F8001 0x7625 PC Begins execution at 0x3F8000 TMS320x2806x Microcontrollers SPRUH18I – JANUARY 2011 – REVISED JUNE 2022 Submit Document Feedback Copyright © 2022 Texas Instruments Incorporated...
Page 217 In 8-bit mode, the LSB of the 16-bit word is read first followed by the MSB. Figure 2-7. Bootloader Basic Transfer Procedure SPRUH18I – JANUARY 2011 – REVISED JUNE 2022 TMS320x2806x Microcontrollers Submit Document Feedback Copyright © 2022 Texas Instruments Incorporated...
Page 218 When selecting a boot mode, the pins should be pulled high or low through a weak pulldown or weak pull-up such that the device can drive them to a new state when required. TMS320x2806x Microcontrollers SPRUH18I – JANUARY 2011 – REVISED JUNE 2022 Submit Document Feedback Copyright © 2022 Texas Instruments Incorporated...
Page 219 *EMU_KEY is Valid and Invalid EMU_MODE *EMU_MODE is Valid. WaitBoot() Return EntryAddr Enable Watchdog Figure 2-9. Overview of the SelectBootMode Function SPRUH18I – JANUARY 2011 – REVISED JUNE 2022 TMS320x2806x Microcontrollers Submit Document Feedback Copyright © 2022 Texas Instruments Incorporated...
Page 220 BlockSize must be less than 0xFFFF for correct operation of the CopyData function. This means the max possible value of BlockSize is 0xFFFE, not 0xFFFF. TMS320x2806x Microcontrollers SPRUH18I – JANUARY 2011 – REVISED JUNE 2022 Submit Document Feedback Copyright © 2022 Texas Instruments Incorporated...
Page 221 After each data transfer, the 28x will echo back the 8-bit character received to the host. In this manner, the host can perform checks that each character was received by the 28x. SPRUH18I – JANUARY 2011 – REVISED JUNE 2022 TMS320x2806x Microcontrollers Submit Document Feedback Copyright © 2022 Texas Instruments Incorporated...
Page 222 Prime SCI-A baud register Read EntryPoint address Enable autobaud detection Call CopyData Autobaud lock Return EntryPoint Figure 2-13. Overview of SCI_Boot Function TMS320x2806x Microcontrollers SPRUH18I – JANUARY 2011 – REVISED JUNE 2022 Submit Document Feedback Copyright © 2022 Texas Instruments Incorporated...
Page 223 (LSB). In this case, data is read from GPIO[31,30,5:0]. The 8-bit data stream is shown in Table 2-11. SPRUH18I – JANUARY 2011 – REVISED JUNE 2022 TMS320x2806x Microcontrollers Submit Document Feedback Copyright © 2022 Texas Instruments Incorporated...
Page 224 This process is repeated for each data value to be sent. Figure 2-17 shows an overview of the Parallel GPIO bootloader flow. TMS320x2806x Microcontrollers SPRUH18I – JANUARY 2011 – REVISED JUNE 2022 Submit Document Feedback Copyright © 2022 Texas Instruments Incorporated...
Page 225 Signal that data Acknowledge 28x is ready (AIO12=1) (AIO12=0) More data End transfer Figure 2-18. Parallel GPIO Mode - Host Transfer Flow SPRUH18I – JANUARY 2011 – REVISED JUNE 2022 TMS320x2806x Microcontrollers Submit Document Feedback Copyright © 2022 Texas Instruments Incorporated...
Page 226 (AIO6 = 1) Host (AIO12 = 1) Host (AIO12 = 1) WordData = MSB:LSB Return WordData Figure 2-19. 8-Bit Parallel GetWord Function TMS320x2806x Microcontrollers SPRUH18I – JANUARY 2011 – REVISED JUNE 2022 Submit Document Feedback Copyright © 2022 Texas Instruments Incorporated...
Page 227 ..Data for this section. Blocks of data in the format size/destination address/data as shown in the generic data stream description SPRUH18I – JANUARY 2011 – REVISED JUNE 2022 TMS320x2806x Microcontrollers Submit Document Feedback Copyright © 2022 Texas Instruments Incorporated...
Page 228 0x0000 is encountered. At that point in time the entry point address is returned to the calling routine that then exits the bootloader and resumes execution at the address specified. TMS320x2806x Microcontrollers SPRUH18I – JANUARY 2011 – REVISED JUNE 2022 Submit Document Feedback Copyright © 2022 Texas Instruments Incorporated...
Page 229 Send dummy SPIA_GetWordData Received character Read LSB Data Send dummy Received character Read MSB Return MSB:LSB Figure 2-22. Overview of SPIA_GetWordData Function SPRUH18I – JANUARY 2011 – REVISED JUNE 2022 TMS320x2806x Microcontrollers Submit Document Feedback Copyright © 2022 Texas Instruments Incorporated...
Page 230 The input frequency to the device must be in the appropriate range. • The EEPROM must be at slave address 0x50. TMS320x2806x Microcontrollers SPRUH18I – JANUARY 2011 – REVISED JUNE 2022 Submit Document Feedback Copyright © 2022 Texas Instruments Incorporated...
Page 231 (I2C_Get Word). If a non acknowledgment is received during the data read messages, the I2C bus will hang. Table 2-13 shows the 8-bit data stream used by the I2C. SPRUH18I – JANUARY 2011 – REVISED JUNE 2022 TMS320x2806x Microcontrollers Submit Document Feedback Copyright © 2022 Texas Instruments Incorporated...
Page 232 Figure 2-25. Random Read SDA LINE 0 0 0 1 0 Device DATA BYTE n DATA BYTE n+1 Address Figure 2-26. Sequential Read TMS320x2806x Microcontrollers SPRUH18I – JANUARY 2011 – REVISED JUNE 2022 Submit Document Feedback Copyright © 2022 Texas Instruments Incorporated...
Page 233 AA first, followed by 08. The program flow of the CAN bootloader is identical to the SCI bootloader. The data sequence for the CAN bootloader is shown in Table 2-15: SPRUH18I – JANUARY 2011 – REVISED JUNE 2022 TMS320x2806x Microcontrollers Submit Document Feedback Copyright © 2022 Texas Instruments Incorporated...
Page 234 Last word of the last block of the source being loaded (More sections if required) Block size of 0000h - indicates end of the source program TMS320x2806x Microcontrollers SPRUH18I – JANUARY 2011 – REVISED JUNE 2022 Submit Document Feedback Copyright © 2022 Texas Instruments Incorporated...
Page 235 After the ExitBoot routine completes and the program flow is redirected to the entry point address, the CPU registers will have the values in Table 2-16. SPRUH18I – JANUARY 2011 – REVISED JUNE 2022 TMS320x2806x Microcontrollers Submit Document Feedback Copyright © 2022 Texas Instruments Incorporated...
Page 236: Building The Boot Table
It can be useful to check this file to make sure that the initialized sections are where you expect them to be. TMS320x2806x Microcontrollers SPRUH18I – JANUARY 2011 – REVISED JUNE 2022 Submit Document Feedback Copyright © 2022 Texas Instruments Incorporated...
Page 237 Specify the value for the I2CCLKL register. This value will be loaded and take effect after all I2C options are loaded, prior to reading data from the EEPROM. SPRUH18I – JANUARY 2011 – REVISED JUNE 2022 TMS320x2806x Microcontrollers Submit Document Feedback Copyright © 2022 Texas Instruments Incorporated...
Page 238 The following command syntax has been used to convert the application into an ASCII hex format file that includes all of the required information for the bootloader. TMS320x2806x Microcontrollers SPRUH18I – JANUARY 2011 – REVISED JUNE 2022 Submit Document Feedback Copyright © 2022 Texas Instruments Incorporated...
Page 239 ;Load block starting at 0x000032 00 00 00 00 ;Data = 0x0000, 0x0000 00 00 ;Block size of 0 - end of data SPRUH18I – JANUARY 2011 – REVISED JUNE 2022 TMS320x2806x Microcontrollers Submit Document Feedback Copyright © 2022 Texas Instruments Incorporated...
Page 240: Bootloader Code Overview
0x3F FFBC Least-significant word of checksum 0x3F FFBD . . . 0x3F FFBE . . . 0x3F FFBF Most-significant word of checksum TMS320x2806x Microcontrollers SPRUH18I – JANUARY 2011 – REVISED JUNE 2022 Submit Document Feedback Copyright © 2022 Texas Instruments Incorporated...
Page 241 Introduction................................242 3.2 ePWM Submodules..............................3.3 Applications to Power Topologies.......................... 3.4 Registers................................... SPRUH18I – JANUARY 2011 – REVISED JUNE 2022 TMS320x2806x Microcontrollers Submit Document Feedback Copyright © 2022 Texas Instruments Incorporated...
Page 242 – Two independent PWM outputs with single-edge operation – Two independent PWM outputs with dual-edge symmetric operation – One independent PWM output with dual-edge asymmetric operation TMS320x2806x Microcontrollers SPRUH18I – JANUARY 2011 – REVISED JUNE 2022 Submit Document Feedback Copyright © 2022 Texas Instruments Incorporated...
Page 243 Each ePWM module consists of eight submodules and is connected within a system with the signals shown in Figure 3-2. SPRUH18I – JANUARY 2011 – REVISED JUNE 2022 TMS320x2806x Microcontrollers Submit Document Feedback Copyright © 2022 Texas Instruments Incorporated...
Page 244 (32 SYSCLKOUT Cycles, Active-Low Output) SPCBx This signal exists only on devices with an eQEP1 module. Figure 3-1. Multiple ePWM Modules TMS320x2806x Microcontrollers SPRUH18I – JANUARY 2011 – REVISED JUNE 2022 Submit Document Feedback Copyright © 2022 Texas Instruments Incorporated...
Page 245 Figure 3-3 also shows the key internal submodule interconnect signals. Each submodule is described in detail in its respective section. SPRUH18I – JANUARY 2011 – REVISED JUNE 2022 TMS320x2806x Microcontrollers Submit Document Feedback Copyright © 2022 Texas Instruments Incorporated...
Page 246 These events are generated by the type 1 ePWM digital compare (DC) submodule based on the levels of the COMPxOUT and TZ signals. This signal exists only on devices with in eQEP1 module. Figure 3-3. ePWM Submodules and Critical Internal Signal Interconnects TMS320x2806x Microcontrollers SPRUH18I – JANUARY 2011 – REVISED JUNE 2022 Submit Document Feedback Copyright © 2022 Texas Instruments Incorporated...
Page 247 High-Resolution Pulse Width Modulator (HRPWM) Extension Registers (2) (3) HRCNFG 0x0020 HRPWM Configuration Register (3) (4) HRPWR 0x0021 HRPWM Power Register SPRUH18I – JANUARY 2011 – REVISED JUNE 2022 TMS320x2806x Microcontrollers Submit Document Feedback Copyright © 2022 Texas Instruments Incorporated...
Page 248 Shadow TBPRDM 0x2B Shadow Active CMPAHR 0x08 Shadow Shadow CMPAHRM 0x2C Shadow TI_Internal CMPA 0x09 Shadow Shadow CMPAM 0x2D Shadow Active TMS320x2806x Microcontrollers SPRUH18I – JANUARY 2011 – REVISED JUNE 2022 Submit Document Feedback Copyright © 2022 Texas Instruments Incorporated...
Page 249 Duty cycle of the second and subsequent pulses. • Bypass the PWM-chopper module entirely. In this case the PWM waveform is passed through without modification. SPRUH18I – JANUARY 2011 – REVISED JUNE 2022 TMS320x2806x Microcontrollers Submit Document Feedback Copyright © 2022 Texas Instruments Incorporated...
Page 250 These examples use the constant definitions in the device EPwm_defines.h file in the device-specific header file and peripheral examples software package. TMS320x2806x Microcontrollers SPRUH18I – JANUARY 2011 – REVISED JUNE 2022 Submit Document Feedback Copyright © 2022 Texas Instruments Incorporated...
Page 251 Configure the rate of the time-base clock; a prescaled version of the CPU system clock (SYSCLKOUT). This allows the time-base counter to increment/decrement at a slower rate. SPRUH18I – JANUARY 2011 – REVISED JUNE 2022 TMS320x2806x Microcontrollers Submit Document Feedback Copyright © 2022 Texas Instruments Incorporated...
Page 252 Prescale TBCTL[HSPCLKDIV] TBCTL[CLKDIV] A. These signals are generated by the digital compare (DC) submodule. Figure 3-5. Time-Base Submodule Signals and Registers TMS320x2806x Microcontrollers SPRUH18I – JANUARY 2011 – REVISED JUNE 2022 Submit Document Feedback Copyright © 2022 Texas Instruments Incorporated...
Page 253 When it reaches zero, the time-base counter is reset to the period value and it begins to decrement once again. SPRUH18I – JANUARY 2011 – REVISED JUNE 2022 TMS320x2806x Microcontrollers Submit Document Feedback Copyright © 2022 Texas Instruments Incorporated...
Page 254 Time-Base Period Immediate Load Mode: If immediate load mode is selected (TBCTL[PRDLD] = 1), then a read from or a write to the TBPRD memory address goes directly to the active register. TMS320x2806x Microcontrollers SPRUH18I – JANUARY 2011 – REVISED JUNE 2022 Submit Document Feedback Copyright © 2022 Texas Instruments Incorporated...
Page 255 GPIO ePWM1 EPWM1SYNCO SYNCI eCAP1 EPWM2SYNCI ePWM2 EPWM2SYNCO EPWM3SYNCI ePWM3 EPWM3SYNCO EPWMxSYNCI ePWMx EPWMxSYNCO Figure 3-7. Time-Base Counter Synchronization Scheme 1 SPRUH18I – JANUARY 2011 – REVISED JUNE 2022 TMS320x2806x Microcontrollers Submit Document Feedback Copyright © 2022 Texas Instruments Incorporated...
Page 256 2. Set TBCLKSYNC = 0. This will stop the time-base clock within any enabled ePWM module. 3. Configure the prescaler values and desired ePWM modes. 4. Set TBCLKSYNC = 1. TMS320x2806x Microcontrollers SPRUH18I – JANUARY 2011 – REVISED JUNE 2022 Submit Document Feedback Copyright © 2022 Texas Instruments Incorporated...
Page 257 0xFFFF TBPRD (value) TBPHS (value) 0000 EPWMxSYNCI CTR_dir CTR = zero CTR = PRD CNT_max Figure 3-8. Time-Base Up-Count Mode Waveforms SPRUH18I – JANUARY 2011 – REVISED JUNE 2022 TMS320x2806x Microcontrollers Submit Document Feedback Copyright © 2022 Texas Instruments Incorporated...
Page 258 DOWN CTR = zero CTR = PRD CNT_max Figure 3-10. Time-Base Up-Down-Count Waveforms, TBCTL[PHSDIR = 0] Count Down On Synchronization Event TMS320x2806x Microcontrollers SPRUH18I – JANUARY 2011 – REVISED JUNE 2022 Submit Document Feedback Copyright © 2022 Texas Instruments Incorporated...
Page 259 CTR = zero CTR = PRD CNT_max Figure 3-11. Time-Base Up-Down Count Waveforms, TBCTL[PHSDIR = 1] Count Up On Synchronization Event SPRUH18I – JANUARY 2011 – REVISED JUNE 2022 TMS320x2806x Microcontrollers Submit Document Feedback Copyright © 2022 Texas Instruments Incorporated...
Page 260 Compare B Active Reg. CTR = 0 CMPB CMPCTL[SHDWBMODE] Compare B Shadow Reg. CMPCTL[LOADBMODE] Figure 3-13. Detailed View of the Counter-Compare Submodule TMS320x2806x Microcontrollers SPRUH18I – JANUARY 2011 – REVISED JUNE 2022 Submit Document Feedback Copyright © 2022 Texas Instruments Incorporated...
Page 261 Time-base counter equal to zero. TBCTR = 0x0000 Used to load active counter-compare A and B registers from the shadow register SPRUH18I – JANUARY 2011 – REVISED JUNE 2022 TMS320x2806x Microcontrollers Submit Document Feedback Copyright © 2022 Texas Instruments Incorporated...
Page 262 To best illustrate the operation of the first three modes, the timing diagrams in Figure 3-14 through Figure 3-17 show when events are generated and how the EPWMxSYNCI signal interacts. TMS320x2806x Microcontrollers SPRUH18I – JANUARY 2011 – REVISED JUNE 2022 Submit Document Feedback Copyright © 2022 Texas Instruments Incorporated...
Page 263 CMPA (value) CMPB (value) TBPHS (value) 0x0000 EPWMxSYNCI CTR = CMPA CTR = CMPB Figure 3-15. Counter-Compare Events in Down-Count Mode SPRUH18I – JANUARY 2011 – REVISED JUNE 2022 TMS320x2806x Microcontrollers Submit Document Feedback Copyright © 2022 Texas Instruments Incorporated...
Page 264 CTR = CMPB CTR = CMPA Figure 3-17. Counter-Compare Events In Up-Down-Count Mode, TBCTL[PHSDIR = 1] Count Up On Synchronization Event TMS320x2806x Microcontrollers SPRUH18I – JANUARY 2011 – REVISED JUNE 2022 Submit Document Feedback Copyright © 2022 Texas Instruments Incorporated...
Page 265 Managing priority when these events occur concurrently • Providing independent control of events when the time-base counter is increasing and when it is decreasing SPRUH18I – JANUARY 2011 – REVISED JUNE 2022 TMS320x2806x Microcontrollers Submit Document Feedback Copyright © 2022 Texas Instruments Incorporated...
Page 266 The event inputs to the action-qualifier submodule are further qualified by the counter direction (up or down). This allows for independent action on outputs on both the count-up and count-down phases. TMS320x2806x Microcontrollers SPRUH18I – JANUARY 2011 – REVISED JUNE 2022 Submit Document Feedback Copyright © 2022 Texas Instruments Incorporated...
Page 267 Comp Comp Zero Period Do Nothing Clear Low Set High Toggle Figure 3-20. Possible Action-Qualifier Actions for EPWMxA and EPWMxB Outputs SPRUH18I – JANUARY 2011 – REVISED JUNE 2022 TMS320x2806x Microcontrollers Submit Document Feedback Copyright © 2022 Texas Instruments Incorporated...
Page 268 If CMPA/CMPB ≤ TBPRD period, then the event occurs Never occurs. on a compare match (TBCTR=CMPA or CMPB). If CMPA/CMPB > TBPRD, then the event will not occur. TMS320x2806x Microcontrollers SPRUH18I – JANUARY 2011 – REVISED JUNE 2022 Submit Document Feedback Copyright © 2022 Texas Instruments Incorporated...
Page 269 0% duty waveform. When CMPA = 0, the PWM signal is high achieving 100% duty. SPRUH18I – JANUARY 2011 – REVISED JUNE 2022 TMS320x2806x Microcontrollers Submit Document Feedback Copyright © 2022 Texas Instruments Incorporated...
Page 270 • Up-Down means Count-up-and-down mode, Up means up-count mode and Dwn means down-count mode • Sym = Symmetric, Asym = Asymmetric TMS320x2806x Microcontrollers SPRUH18I – JANUARY 2011 – REVISED JUNE 2022 Submit Document Feedback Copyright © 2022 Texas Instruments Incorporated...
Page 271 // = = = = = = = = = = = = = = = = = = = = = = = = EPwm1Regs.CMPA.half.CMPA = Duty1A; // adjust duty for output EPWM1A EPwm1Regs.CMPB = Duty1B; // adjust duty for output EPWM1B SPRUH18I – JANUARY 2011 – REVISED JUNE 2022 TMS320x2806x Microcontrollers Submit Document Feedback Copyright © 2022 Texas Instruments Incorporated...
Page 272 Actions at zero and period, although appearing to occur concurrently, are actually separated by one TBCLK period. TBCTR wraps from period to 0000. Figure 3-23. Up, Single Edge Asymmetric Waveform With Independent Modulation on EPWMxA and EPWMxB—Active Low TMS320x2806x Microcontrollers SPRUH18I – JANUARY 2011 – REVISED JUNE 2022 Submit Document Feedback Copyright © 2022 Texas Instruments Incorporated...
Page 273 // = = = = = = = = = = = = = = = = = = = = = = = = EPwm1Regs.CMPA.half.CMPA = Duty1A; // adjust duty for output EPWM1A EPwm1Regs.CMPB = Duty1B; // adjust duty for output EPWM1B SPRUH18I – JANUARY 2011 – REVISED JUNE 2022 TMS320x2806x Microcontrollers Submit Document Feedback Copyright © 2022 Texas Instruments Incorporated...
Page 274 // = = = = = = = = = = = = = = = = = = = = = = = = EPwm1Regs.CMPA.half.CMPA = EdgePosA; // adjust duty for output EPWM1A only EPwm1Regs.CMPB = EdgePosB; TMS320x2806x Microcontrollers SPRUH18I – JANUARY 2011 – REVISED JUNE 2022 Submit Document Feedback Copyright © 2022 Texas Instruments Incorporated...
Page 275 // = = = = = = = = = = = = = = = = = = = = = = = = EPwm1Regs.CMPA.half.CMPA = Duty1A; // adjust duty for output EPWM1A EPwm1Regs.CMPB = Duty1B; // adjust duty for output EPWM1B SPRUH18I – JANUARY 2011 – REVISED JUNE 2022 TMS320x2806x Microcontrollers Submit Document Feedback Copyright © 2022 Texas Instruments Incorporated...
Page 276 // = = = = = = = = = = = = = = = = = = = = = = = = EPwm1Regs.CMPA.half.CMPA = Duty1A; // adjust duty for output EPWM1A EPwm1Regs.CMPB = Duty1B; // adjust duty for output EPWM1B TMS320x2806x Microcontrollers SPRUH18I – JANUARY 2011 – REVISED JUNE 2022 Submit Document Feedback Copyright © 2022 Texas Instruments Incorporated...
Page 277 // = = = = = = = = = = = = = = = = = = = = = = = = EPwm1Regs.CMPA.half.CMPA = EdgePosA; // adjust duty for output EPWM1A only EPwm1Regs.CMPB = EdgePosB; SPRUH18I – JANUARY 2011 – REVISED JUNE 2022 TMS320x2806x Microcontrollers Submit Document Feedback Copyright © 2022 Texas Instruments Incorporated...
Page 278 Section 3.4.4.1 DBRED 0x0010 Dead-Band Rising Edge Delay Count Register Section 3.4.4.2 DBFED 0x0011 Dead-Band Falling Edge Delay Count Register Section 3.4.4.3 TMS320x2806x Microcontrollers SPRUH18I – JANUARY 2011 – REVISED JUNE 2022 Submit Document Feedback Copyright © 2022 Texas Instruments Incorporated...
Page 279 3-30. Note that to generate equivalent waveforms to Figure 3-30, configure the action-qualifier submodule to generate the signal as shown for EPWMxA. SPRUH18I – JANUARY 2011 – REVISED JUNE 2022 TMS320x2806x Microcontrollers Submit Document Feedback Copyright © 2022 Texas Instruments Incorporated...
Page 280 FED = DBFED × T TBCLK RED = DBRED × T TBCLK Figure 3-30 shows waveforms for typical cases where 0% < duty < 100%. TMS320x2806x Microcontrollers SPRUH18I – JANUARY 2011 – REVISED JUNE 2022 Submit Document Feedback Copyright © 2022 Texas Instruments Incorporated...
Page 281 Active Low Complementary (ALC) Active High (AH) Active Low (AL) Figure 3-30. Dead-Band Waveforms for Typical Cases (0% < Duty < 100%) SPRUH18I – JANUARY 2011 – REVISED JUNE 2022 TMS320x2806x Microcontrollers Submit Document Feedback Copyright © 2022 Texas Instruments Incorporated...
Page 282 The one-shot width is programmed via the OSHTWTH bits. The PWM-chopper submodule can be fully disabled (bypassed) via the CHPEN bit. TMS320x2806x Microcontrollers SPRUH18I – JANUARY 2011 – REVISED JUNE 2022 Submit Document Feedback Copyright © 2022 Texas Instruments Incorporated...
Page 283 Details of the one-shot and duty-cycle control are discussed in the following sections. EPWMxA EPWMxB PSCLK EPWMxA EPWMxB Figure 3-33. Simple PWM-Chopper Submodule Waveforms Showing Chopping Action Only SPRUH18I – JANUARY 2011 – REVISED JUNE 2022 TMS320x2806x Microcontrollers Submit Document Feedback Copyright © 2022 Texas Instruments Incorporated...
Page 284 Table 3-16. Possible Pulse Width Values for SYSCLKOUT = 90 MHz OSHTWTHz Pulse Width (hex) (nS) 1067 1156 1244 1333 1422 TMS320x2806x Microcontrollers SPRUH18I – JANUARY 2011 – REVISED JUNE 2022 Submit Document Feedback Copyright © 2022 Texas Instruments Incorporated...
Page 285 Duty Duty Duty Duty Duty Duty Figure 3-35. PWM-Chopper Submodule Waveforms Showing the Pulse Width (Duty Cycle) Control of Sustaining Pulses SPRUH18I – JANUARY 2011 – REVISED JUNE 2022 TMS320x2806x Microcontrollers Submit Document Feedback Copyright © 2022 Texas Instruments Incorporated...
Page 286 Interrupt generation is possible on any trip-zone input. • Software-forced tripping is also supported. • The trip-zone submodule can be fully bypassed if it is not required. TMS320x2806x Microcontrollers SPRUH18I – JANUARY 2011 – REVISED JUNE 2022 Submit Document Feedback Copyright © 2022 Texas Instruments Incorporated...
Page 287 TZCLR[CBC] bit. If the cycle-by-cycle trip event is still present when the TZFLG[CBC] bit is cleared, then it will again be immediately set. SPRUH18I – JANUARY 2011 – REVISED JUNE 2022 TMS320x2806x Microcontrollers Submit Document Feedback Copyright © 2022 Texas Instruments Incorporated...
Page 288 Force to High State Tripped Force to Low State Tripped No Change Do Nothing. No change is made to the output. TMS320x2806x Microcontrollers SPRUH18I – JANUARY 2011 – REVISED JUNE 2022 Submit Document Feedback Copyright © 2022 Texas Instruments Incorporated...
Page 289 – TZCTL[TZA] = 0: EPWM2A will be put into a high-impedance state on a trip event. – TZCTL[TZB] = 3: EPWM2B will ignore the trip event. SPRUH18I – JANUARY 2011 – REVISED JUNE 2022 TMS320x2806x Microcontrollers Submit Document Feedback Copyright © 2022 Texas Instruments Incorporated...
Page 290 Clear Trip TZFLG[OST] DCAEVT1.force One-Shot (OSHT) DCBEVT1.force Trip Events TZSEL[OSHT1 to OSHT6, DCAEVT1, DCBEVT1] Figure 3-37. Trip-Zone Submodule Mode Control Logic TMS320x2806x Microcontrollers SPRUH18I – JANUARY 2011 – REVISED JUNE 2022 Submit Document Feedback Copyright © 2022 Texas Instruments Incorporated...
Page 291 Latch DCAEVT2.inter TZEINT[DCAEVT2] TZFLG[DCBEVT1] Clear TZCLR[DCBEVT1] Latch DCBEVT1.inter TZEINT[DCBEVT1] TZFLG[DCBEVT2] Clear TZCLR[DCBEVT2] Latch DCBEVT2.inter TZEINT[DCBEVT2] Figure 3-38. Trip-Zone Submodule Interrupt Logic SPRUH18I – JANUARY 2011 – REVISED JUNE 2022 TMS320x2806x Microcontrollers Submit Document Feedback Copyright © 2022 Texas Instruments Incorporated...
Page 292 ADC trigger inputs to the ADC, and hence multiple modules can initiate an ADC start of conversion via the ADC trigger inputs. TMS320x2806x Microcontrollers SPRUH18I – JANUARY 2011 – REVISED JUNE 2022 Submit Document Feedback Copyright © 2022 Texas Instruments Incorporated...
Page 293 EPWMxSOCB DCAEVT1.soc From Digital Compare count ETFRC reg DCBEVT1.soc (DC) Submodule Figure 3-41. Event-Trigger Submodule Showing Event Inputs and Prescaled Outputs SPRUH18I – JANUARY 2011 – REVISED JUNE 2022 TMS320x2806x Microcontrollers Submit Document Feedback Copyright © 2022 Texas Instruments Incorporated...
Page 294 If interrupts are enabled, but the interrupt flag is already set, then the counter will hold its output high until the ETFLG[INT] flag is cleared. This allows for one interrupt to be pending while one is serviced. TMS320x2806x Microcontrollers SPRUH18I – JANUARY 2011 – REVISED JUNE 2022 Submit Document Feedback Copyright © 2022 Texas Instruments Incorporated...
Page 295 2-bit ETFRC[INT] Input = 1 Counter CTR=Zero CTR=PRD Inc CNT ETSEL[INT] CTRU=CMPA CTRD=CMPA ETPS[INTPRD] CTRU=CMPB CTRD=CMPB Figure 3-42. Event-Trigger Interrupt Generator SPRUH18I – JANUARY 2011 – REVISED JUNE 2022 TMS320x2806x Microcontrollers Submit Document Feedback Copyright © 2022 Texas Instruments Incorporated...
Page 296 The DCBEVT1.soc signals are signals generated by the Digital compare (DC) submodule described later in Section 3.2.9 Figure 3-44. Event-Trigger SOCB Pulse Generator TMS320x2806x Microcontrollers SPRUH18I – JANUARY 2011 – REVISED JUNE 2022 Submit Document Feedback Copyright © 2022 Texas Instruments Incorporated...
Page 297 – generate a synchronization event for synchronizing the ePWM module TBCTR. • Event filtering (blanking window logic) can optionally blank the input signal to remove noise. SPRUH18I – JANUARY 2011 – REVISED JUNE 2022 TMS320x2806x Microcontrollers Submit Document Feedback Copyright © 2022 Texas Instruments Incorporated...
Page 298 The priority of conflicting actions on the TZCTL register is as follows (highest priority overrides lower priority): – Output EPWMxA: TZA (highest) -> DCAEVT1 -> DCAEVT2 (lowest) – Output EPWMxB: TZB (highest) -> DCBEVT1 -> DCBEVT2 (lowest) TMS320x2806x Microcontrollers SPRUH18I – JANUARY 2011 – REVISED JUNE 2022 Submit Document Feedback Copyright © 2022 Texas Instruments Incorporated...
Page 299 Figure 3-46. DCAEVT1 Event Triggering DCACTL[EVT2SRCSEL] DCACTL[EVT2FRCSYNCSEL] DCEVTFILT Async DCAEVT2 DCAEVT2.force Sync TZEINT[DCAEVT2] TBCLK TZFRC[DCAEVT2] Latch DCAEVT2.inter Clear TZFLG[DCAEVT2] TZCLR[DCAEVT2] Figure 3-47. DCAEVT2 Event Triggering SPRUH18I – JANUARY 2011 – REVISED JUNE 2022 TMS320x2806x Microcontrollers Submit Document Feedback Copyright © 2022 Texas Instruments Incorporated...
Page 300 Figure 3-48. DCBEVT1 Event Triggering DCBCTL[EVT2SRCSEL] DCBCTL[EVT2FRCSYNCSEL] DCEVTFILT async DCBEVT2 Sync DCBEVT2.force TBCLK TZEINT[DCBEVT2] Latch DCBEVT2.inter clear TZCLR[DCBEVT2] TZFLG[DCBEVT2] TZFRC[DCBEVT2] Figure 3-49. DCBEVT2 Event Triggering TMS320x2806x Microcontrollers SPRUH18I – JANUARY 2011 – REVISED JUNE 2022 Submit Document Feedback Copyright © 2022 Texas Instruments Incorporated...
Page 301 Notice that if the blanking window crosses the CTR = 0 or CTR = PRD boundary, the next window still starts at the same offset value after the CTR = 0 or CTR = PRD pulse. SPRUH18I – JANUARY 2011 – REVISED JUNE 2022 TMS320x2806x Microcontrollers Submit Document Feedback Copyright © 2022 Texas Instruments Incorporated...
Page 302 SyncIn Phase reg EPWMxA Φ=0° EPWMxB CTR = 0 CTR=CMPB SyncOut Figure 3-52. Simplified ePWM Module TMS320x2806x Microcontrollers SPRUH18I – JANUARY 2011 – REVISED JUNE 2022 Submit Document Feedback Copyright © 2022 Texas Instruments Incorporated...
Page 303 EPWM1B EPWM2B CTR=0 CTR=0 CTR=CMPB CTR=CMPB SyncOut SyncOut Figure 3-53. EPWM1 Configured as a Typical Master, EPWM2 Configured as a Slave SPRUH18I – JANUARY 2011 – REVISED JUNE 2022 TMS320x2806x Microcontrollers Submit Document Feedback Copyright © 2022 Texas Instruments Incorporated...
Page 304 Θ = X indicates value in phase register is a "don't care" Figure 3-54. Control of Four Buck Stages. Here F ≠ F ≠ F ≠ F PWM1 PWM2 PWM3 PWM4 TMS320x2806x Microcontrollers SPRUH18I – JANUARY 2011 – REVISED JUNE 2022 Submit Document Feedback Copyright © 2022 Texas Instruments Incorporated...
Page 305 Indicates this event triggers an interrupt of conversion Figure 3-55. Buck Waveforms for Figure 3-54 (Note: Only three bucks shown here) SPRUH18I – JANUARY 2011 – REVISED JUNE 2022 TMS320x2806x Microcontrollers Submit Document Feedback Copyright © 2022 Texas Instruments Incorporated...
Page 306 // adjust duty for output EPWM1A EPwm2Regs.CMPA.half.CMPA = 700; // adjust duty for output EPWM2A EPwm3Regs.CMPA.half.CMPA = 500; // adjust duty for output EPWM3A TMS320x2806x Microcontrollers SPRUH18I – JANUARY 2011 – REVISED JUNE 2022 Submit Document Feedback Copyright © 2022 Texas Instruments Incorporated...
Page 307 CTR=zero CTR=CMPB Buck #4 SyncOut EPWM2B Figure 3-56. Control of Four Buck Stages. (Note: F = N x F PWM2 PWM1 SPRUH18I – JANUARY 2011 – REVISED JUNE 2022 TMS320x2806x Microcontrollers Submit Document Feedback Copyright © 2022 Texas Instruments Incorporated...
Page 308 Enhanced Pulse Width Modulator (ePWM) Module www.ti.com EPWM1A EPWM1B EPWM2A EPWM2B Figure 3-57. Buck Waveforms for Figure 3-56 (Note: F PWM2 PWM1) TMS320x2806x Microcontrollers SPRUH18I – JANUARY 2011 – REVISED JUNE 2022 Submit Document Feedback Copyright © 2022 Texas Instruments Incorporated...
Page 309 // adjust duty for output EPWM1B EPwm2Regs.CMPA.half.CMPA = 500; // adjust duty for output EPWM2A EPwm2Regs.CMPB = 300; // adjust duty for output EPWM2B SPRUH18I – JANUARY 2011 – REVISED JUNE 2022 TMS320x2806x Microcontrollers Submit Document Feedback Copyright © 2022 Texas Instruments Incorporated...
Page 310 EPWM2B CTR=zero EPWM2A CTR=CMPB SyncOut EPWM2B Figure 3-58. Control of Two Half-H Bridge Stages (F = N x F PWM2 PWM1 TMS320x2806x Microcontrollers SPRUH18I – JANUARY 2011 – REVISED JUNE 2022 Submit Document Feedback Copyright © 2022 Texas Instruments Incorporated...
Page 311 EPWM2A RED Delay RED Delay EPWM2B Pulse Center Figure 3-59. Half-H Bridge Waveforms for Figure 3-58 (Note: Here F PWM2 PWM1 SPRUH18I – JANUARY 2011 – REVISED JUNE 2022 TMS320x2806x Microcontrollers Submit Document Feedback Copyright © 2022 Texas Instruments Incorporated...
Page 312 (module 1) and five slaves. In this case, the frequency of modules 4, 5, and 6 (all equal) can be integer multiples of the frequency for modules 1, 2, 3 (also all equal). TMS320x2806x Microcontrollers SPRUH18I – JANUARY 2011 – REVISED JUNE 2022 Submit Document Feedback Copyright © 2022 Texas Instruments Incorporated...
Page 313 EPWM6A Φ=0° EPWM6B CTR=zero CTR=CMPB SyncOut Figure 3-60. Control of Dual 3-Phase Inverter Stages as Is Commonly Used in Motor Control SPRUH18I – JANUARY 2011 – REVISED JUNE 2022 TMS320x2806x Microcontrollers Submit Document Feedback Copyright © 2022 Texas Instruments Incorporated...
Page 314 EPWM1A EPWM1B Φ2=0 EPWM2A EPWM2B Φ3=0 EPWM3A EPWM3B Figure 3-61. 3-Phase Inverter Waveforms for Figure 3-60 (Only One Inverter Shown) TMS320x2806x Microcontrollers SPRUH18I – JANUARY 2011 – REVISED JUNE 2022 Submit Document Feedback Copyright © 2022 Texas Instruments Incorporated...
Page 315 // adjust duty for output EPWM1A EPwm2Regs.CMPA.half.CMPA = 600; // adjust duty for output EPWM2A EPwm3Regs.CMPA.half.CMPA = 700; // adjust duty for output EPWM3A SPRUH18I – JANUARY 2011 – REVISED JUNE 2022 TMS320x2806x Microcontrollers Submit Document Feedback Copyright © 2022 Texas Instruments Incorporated...
Page 316 CTR=CMPB SyncOut Slave Phase reg SyncIn EPWM2A Φ=120° EPWM2B CTR=zero CTR=CMPB SyncOut Figure 3-62. Configuring Two PWM Modules for Phase Control TMS320x2806x Microcontrollers SPRUH18I – JANUARY 2011 – REVISED JUNE 2022 Submit Document Feedback Copyright © 2022 Texas Instruments Incorporated...
Page 317 Phase = 120° Φ2 Slave Module TBPRD TBPHS 0000 SyncIn time Figure 3-63. Timing Waveforms Associated With Phase Control Between 2 Modules SPRUH18I – JANUARY 2011 – REVISED JUNE 2022 TMS320x2806x Microcontrollers Submit Document Feedback Copyright © 2022 Texas Instruments Incorporated...
Page 318 CTR=CMPB SyncOut Slave Phase reg SyncIn EPWM3A Φ=240° EPWM3B CTR=zero CTR=CMPB SyncOut Figure 3-64. Control of a 3-Phase Interleaved DC/DC Converter TMS320x2806x Microcontrollers SPRUH18I – JANUARY 2011 – REVISED JUNE 2022 Submit Document Feedback Copyright © 2022 Texas Instruments Incorporated...
Page 319 ° TBPHS (=300) EPWM2A EPWM2B 2=120 ° TBPHS (=300) EPWM3A EPWM3B Figure 3-65. 3-Phase Interleaved DC/DC Converter Waveforms for Figure 3-64 SPRUH18I – JANUARY 2011 – REVISED JUNE 2022 TMS320x2806x Microcontrollers Submit Document Feedback Copyright © 2022 Texas Instruments Incorporated...
Page 320 // adjust duty for output EPWM1A EPwm2Regs.CMPA.half.CMPA = 285; // adjust duty for output EPWM2A EPwm3Regs.CMPA.half.CMPA = 285; // adjust duty for output EPWM3A TMS320x2806x Microcontrollers SPRUH18I – JANUARY 2011 – REVISED JUNE 2022 Submit Document Feedback Copyright © 2022 Texas Instruments Incorporated...
Page 321 EPWM2A Φ=Var° EPWM1B EPWM2B EPWM2B CTR=zero CTR=CMPB SyncOut Var = Variable Figure 3-66. Controlling a Full-H Bridge Stage (F PWM2 PWM1) SPRUH18I – JANUARY 2011 – REVISED JUNE 2022 TMS320x2806x Microcontrollers Submit Document Feedback Copyright © 2022 Texas Instruments Incorporated...
Page 322 EPWM1A ZVS transition Power phase EPWM1B ZVS transition Φ2=variable TBPHS =(1200−Φ2) EPWM2A EPWM2B Power phase Figure 3-67. ZVS Full-H Bridge Waveforms TMS320x2806x Microcontrollers SPRUH18I – JANUARY 2011 – REVISED JUNE 2022 Submit Document Feedback Copyright © 2022 Texas Instruments Incorporated...
Page 323 // Update ZVS transition interval EPwm2Regs.DBRED = RED2_NewValue; // Update ZVS transition interval EPwm1Regs.CMPB = 200; // Adjust point-in-time for ADCSOC trigger SPRUH18I – JANUARY 2011 – REVISED JUNE 2022 TMS320x2806x Microcontrollers Submit Document Feedback Copyright © 2022 Texas Instruments Incorporated...
Page 324 Time base Increased Reference DAC OUT/ DAC Out COMP1- Isense DCAEVT2.force ePWM1A Figure 3-69. Peak Current Mode Control Waveforms for Figure 3-68 TMS320x2806x Microcontrollers SPRUH18I – JANUARY 2011 – REVISED JUNE 2022 Submit Document Feedback Copyright © 2022 Texas Instruments Incorporated...
Page 325 EPwm1Regs.TZCTL.bit.TZA = TZ_FORCE_LO; // EPWM1A will go low //=========================================================================== // Run Time //=========================================================================== // Adjust reference peak current to Comparator 1 negative input SPRUH18I – JANUARY 2011 – REVISED JUNE 2022 TMS320x2806x Microcontrollers Submit Document Feedback Copyright © 2022 Texas Instruments Incorporated...
Page 326 Indicates this event triggers an ADC Indicates this event triggers an interrupt start of conversion Figure 3-71. H-Bridge LLC Resonant Converter PWM Waveforms TMS320x2806x Microcontrollers SPRUH18I – JANUARY 2011 – REVISED JUNE 2022 Submit Document Feedback Copyright © 2022 Texas Instruments Incorporated...
Page 327 // value/2; // Update new CMPA EPwm1Regs.CMPB= period_new // value/4; // Update new CMPB // Update new CMPB // Update new CMPB SPRUH18I – JANUARY 2011 – REVISED JUNE 2022 TMS320x2806x Microcontrollers Submit Document Feedback Copyright © 2022 Texas Instruments Incorporated...
Page 328 These bits determine part of the time-base clock prescale value. TBCLK = SYSCLKOUT / (HSPCLKDIV × CLKDIV) /1 (default on reset) /128 TMS320x2806x Microcontrollers SPRUH18I – JANUARY 2011 – REVISED JUNE 2022 Submit Document Feedback Copyright © 2022 Texas Instruments Incorporated...
Page 329 These bits set the time-base counter mode of operation as follows: Up-count mode Down-count mode Up-down-count mode Stop-freeze counter operation (default on reset) SPRUH18I – JANUARY 2011 – REVISED JUNE 2022 TMS320x2806x Microcontrollers Submit Document Feedback Copyright © 2022 Texas Instruments Incorporated...
Page 330 To make this bit meaningful, you must first set the appropriate mode via TBCTL[CTRMODE]. Time-Base Counter is currently counting down. Time-Base Counter is currently counting up. TMS320x2806x Microcontrollers SPRUH18I – JANUARY 2011 – REVISED JUNE 2022 Submit Document Feedback Copyright © 2022 Texas Instruments Incorporated...
Page 331 The synchronization event can be initiated by the input synchronization signal (EPWMxSYNCI) or by a software forced synchronization. SPRUH18I – JANUARY 2011 – REVISED JUNE 2022 TMS320x2806x Microcontrollers Submit Document Feedback Copyright © 2022 Texas Instruments Incorporated...
Page 332 • The active and shadow registers share the same memory map address. TMS320x2806x Microcontrollers SPRUH18I – JANUARY 2011 – REVISED JUNE 2022 Submit Document Feedback Copyright © 2022 Texas Instruments Incorporated...
Page 333 This register is only available with ePWM modules which support high-resolution period control. Reserved Reserved SPRUH18I – JANUARY 2011 – REVISED JUNE 2022 TMS320x2806x Microcontrollers Submit Document Feedback Copyright © 2022 Texas Instruments Incorporated...
Page 334 The TBPRDHRM register is available with ePWM modules which support high-resolution period control and is used only when the high resolution period feature is enabled. Reserved 00-FFh Reserved for TI Test TMS320x2806x Microcontrollers SPRUH18I – JANUARY 2011 – REVISED JUNE 2022 Submit Document Feedback Copyright © 2022 Texas Instruments Incorporated...
Page 335 If TBCTL[PRDLD] = 1, then the shadow is disabled and any write to this register will go directly to the active register controlling the hardware. Likewise reads return the active value. SPRUH18I – JANUARY 2011 – REVISED JUNE 2022 TMS320x2806x Microcontrollers Submit Document Feedback Copyright © 2022 Texas Instruments Incorporated...
Page 336 Load on CTR = PRD: Time-base counter equal to period (TBCTR = TBPRD) Load on either CTR = Zero or CTR = PRD Freeze (no loads possible) TMS320x2806x Microcontrollers SPRUH18I – JANUARY 2011 – REVISED JUNE 2022 Submit Document Feedback Copyright © 2022 Texas Instruments Incorporated...
Page 337 CMPA:CMPAHR can be accessed in a single 32-bit read/write. Shadowing is enabled and disabled by the CMPCTL[SHDWAMODE] bit as described for the CMPA register. Reserved Reserved for TI Test SPRUH18I – JANUARY 2011 – REVISED JUNE 2022 TMS320x2806x Microcontrollers Submit Document Feedback Copyright © 2022 Texas Instruments Incorporated...
Page 338 • In either mode, the active and shadow registers share the same memory map address. TMS320x2806x Microcontrollers SPRUH18I – JANUARY 2011 – REVISED JUNE 2022 Submit Document Feedback Copyright © 2022 Texas Instruments Incorporated...
Page 339 • In either mode, the active and shadow registers share the same memory map address. SPRUH18I – JANUARY 2011 – REVISED JUNE 2022 TMS320x2806x Microcontrollers Submit Document Feedback Copyright © 2022 Texas Instruments Incorporated...
Page 340 By default writes to this register are shadowed. Shadowing is enabled and disabled by the CMPCTL[SHDWAMODE] bit as described for the CMPAM register. Reserved Reserved for TI Test TMS320x2806x Microcontrollers SPRUH18I – JANUARY 2011 – REVISED JUNE 2022 Submit Document Feedback Copyright © 2022 Texas Instruments Incorporated...
Page 341 If CMPCTL[SHDWAMODE] = 1, then the shadow register is disabled and any write will go directly to the active register, that is the register actively controlling the hardware. SPRUH18I – JANUARY 2011 – REVISED JUNE 2022 TMS320x2806x Microcontrollers Submit Document Feedback Copyright © 2022 Texas Instruments Incorporated...
Page 342 Set: force EPWMxA output high. Toggle EPWMxA output: low output signal will be forced high, and a high signal will be forced low. TMS320x2806x Microcontrollers SPRUH18I – JANUARY 2011 – REVISED JUNE 2022 Submit Document Feedback Copyright © 2022 Texas Instruments Incorporated...
Page 343 Set: force EPWMxB output high. Toggle EPWMxB output: low output signal will be forced high, and a high signal will be forced low. SPRUH18I – JANUARY 2011 – REVISED JUNE 2022 TMS320x2806x Microcontrollers Submit Document Feedback Copyright © 2022 Texas Instruments Incorporated...
Page 344 Set: force EPWMxB output high. Toggle EPWMxB output: low output signal will be forced high, and a high signal will be forced low. TMS320x2806x Microcontrollers SPRUH18I – JANUARY 2011 – REVISED JUNE 2022 Submit Document Feedback Copyright © 2022 Texas Instruments Incorporated...
Page 345 Clear (low) Set (high) Toggle (Low → High, High → Low) Note: This action is not qualified by counter direction (CNT_dir) SPRUH18I – JANUARY 2011 – REVISED JUNE 2022 TMS320x2806x Microcontrollers Submit Document Feedback Copyright © 2022 Texas Instruments Incorporated...
Page 346 Forces a continuous low on output A Forces a continuous high on output A Software forcing is disabled and has no effect TMS320x2806x Microcontrollers SPRUH18I – JANUARY 2011 – REVISED JUNE 2022 Submit Document Feedback Copyright © 2022 Texas Instruments Incorporated...
Page 347 Active low complementary (ALC) mode. EPWMxA is inverted. Active high complementary (AHC). EPWMxB is inverted. Active low (AL) mode. Both EPWMxA and EPWMxB are inverted. SPRUH18I – JANUARY 2011 – REVISED JUNE 2022 TMS320x2806x Microcontrollers Submit Document Feedback Copyright © 2022 Texas Instruments Incorporated...
Page 348 Dead-band is fully enabled for both rising-edge delay on output EPWMxA and falling-edge delay on output EPWMxB. The input signal for the delay is determined by DBCTL[IN_MODE]. TMS320x2806x Microcontrollers SPRUH18I – JANUARY 2011 – REVISED JUNE 2022 Submit Document Feedback Copyright © 2022 Texas Instruments Incorporated...
Page 349 Table 3-42. Dead-Band Generator Falling Edge Delay (DBFED) Register Field Descriptions Bits Name Description 15-10 Reserved Reserved Falling Edge Delay Count. 10-bit counter SPRUH18I – JANUARY 2011 – REVISED JUNE 2022 TMS320x2806x Microcontrollers Submit Document Feedback Copyright © 2022 Texas Instruments Incorporated...
Page 350 Disable TZ1 as a one-shot trip source for this ePWM module Enable TZ1 as a one-shot trip source for this ePWM module TMS320x2806x Microcontrollers SPRUH18I – JANUARY 2011 – REVISED JUNE 2022 Submit Document Feedback Copyright © 2022 Texas Instruments Incorporated...
Page 351 LEGEND: R/W = Read/Write; R = Read only; -n = value after reset Table 3-44. Trip Zone Digital Compare Event Select Register (TZDCSEL) Field Descriptions Field Value Description 15-12 Reserved Reserved SPRUH18I – JANUARY 2011 – REVISED JUNE 2022 TMS320x2806x Microcontrollers Submit Document Feedback Copyright © 2022 Texas Instruments Incorporated...
Page 352 DCAL = low, DCAH = don't care DCAL = high, DCAH = don't care DCAL = high, DCAH = low reserved reserved TMS320x2806x Microcontrollers SPRUH18I – JANUARY 2011 – REVISED JUNE 2022 Submit Document Feedback Copyright © 2022 Texas Instruments Incorporated...
Page 353 High-impedance (EPWMxB = High-impedance state) Force EPWMxB to a high state Force EPWMxB to a low state Do nothing, no action is taken on EPWMxB. SPRUH18I – JANUARY 2011 – REVISED JUNE 2022 TMS320x2806x Microcontrollers Submit Document Feedback Copyright © 2022 Texas Instruments Incorporated...
Page 354 Trip-zone Cycle-by-Cycle Interrupt Enable Disable cycle-by-cycle interrupt generation. Enable interrupt generation; a cycle-by-cycle trip event will cause an EPWMx_TZINT PIE interrupt. Reserved Reserved TMS320x2806x Microcontrollers SPRUH18I – JANUARY 2011 – REVISED JUNE 2022 Submit Document Feedback Copyright © 2022 Texas Instruments Incorporated...
Page 355 TBCTR = 0x0000 no matter where in the cycle the CBC flag is cleared. This bit is cleared by writing the appropriate value to the TZCLR register . SPRUH18I – JANUARY 2011 – REVISED JUNE 2022 TMS320x2806x Microcontrollers Submit Document Feedback Copyright © 2022 Texas Instruments Incorporated...
Page 356 Clearing all flag bits will prevent further interrupts. This bit is cleared by writing the appropriate value to the TZCLR register . TMS320x2806x Microcontrollers SPRUH18I – JANUARY 2011 – REVISED JUNE 2022 Submit Document Feedback Copyright © 2022 Texas Instruments Incorporated...
Page 357 TZFLG[INT] bit is cleared and any of the other flag bits are set, then another interrupt pulse will be generated. Clearing all flag bits will prevent further interrupts. SPRUH18I – JANUARY 2011 – REVISED JUNE 2022 TMS320x2806x Microcontrollers Submit Document Feedback Copyright © 2022 Texas Instruments Incorporated...
Page 358 Writing of 0 is ignored. Always reads back a 0. Forces a cycle-by-cycle trip event and sets the TZFLG[CBC] bit. Reserved Reserved TMS320x2806x Microcontrollers SPRUH18I – JANUARY 2011 – REVISED JUNE 2022 Submit Document Feedback Copyright © 2022 Texas Instruments Incorporated...
Page 359 Enable event: time-base counter equal to CMPB when the timer is incrementing. Enable event: time-base counter equal to CMPB when the timer is decrementing. Reserved Reserved SPRUH18I – JANUARY 2011 – REVISED JUNE 2022 TMS320x2806x Microcontrollers Submit Document Feedback Copyright © 2022 Texas Instruments Incorporated...
Page 360 Generate the EPWMxSOCB pulse on the second event: ETPS[SOCBCNT] = 1,0 Generate the EPWMxSOCB pulse on the third event: ETPS[SOCBCNT] = 1,1 TMS320x2806x Microcontrollers SPRUH18I – JANUARY 2011 – REVISED JUNE 2022 Submit Document Feedback Copyright © 2022 Texas Instruments Incorporated...
Page 361 Generate an interrupt on the first event INTCNT = 01 (first event) Generate interrupt on ETPS[INTCNT] = 1,0 (second event) Generate interrupt on ETPS[INTCNT] = 1,1 (third event) SPRUH18I – JANUARY 2011 – REVISED JUNE 2022 TMS320x2806x Microcontrollers Submit Document Feedback Copyright © 2022 Texas Instruments Incorporated...
Page 362 If an interrupt is pending, it will not be generated until after the ETFLG[INT] bit is cleared. Figure 3-42. TMS320x2806x Microcontrollers SPRUH18I – JANUARY 2011 – REVISED JUNE 2022 Submit Document Feedback Copyright © 2022 Texas Instruments Incorporated...
Page 363 Writing a 0 has no effect. Always reads back a 0 Clears the ETFLG[INT] flag bit and enable further interrupts pulses to be generated SPRUH18I – JANUARY 2011 – REVISED JUNE 2022 TMS320x2806x Microcontrollers Submit Document Feedback Copyright © 2022 Texas Instruments Incorporated...
Page 364 Writing 0 to this bit will be ignored. Always reads back a 0. Generates an interrupt on EPWMxINT and set the INT flag bit. This bit is used for test purposes. TMS320x2806x Microcontrollers SPRUH18I – JANUARY 2011 – REVISED JUNE 2022 Submit Document Feedback Copyright © 2022 Texas Instruments Incorporated...
Page 365 Divide by 6 (1.88 MHz at 90 MHz SYSCLKOUT) Divide by 7 (1.61 MHz at 90 MHz SYSCLKOUT) Divide by 8 (1.41 MHz at 90 MHz SYSCLKOUT) SPRUH18I – JANUARY 2011 – REVISED JUNE 2022 TMS320x2806x Microcontrollers Submit Document Feedback Copyright © 2022 Texas Instruments Incorporated...
Page 366 16 x SYSCLKOUT / 8 wide ( = 1422 nS at 90 MHz SYSCLKOUT) CHPEN PWM-chopping Enable Disable (bypass) PWM chopping function Enable chopping function TMS320x2806x Microcontrollers SPRUH18I – JANUARY 2011 – REVISED JUNE 2022 Submit Document Feedback Copyright © 2022 Texas Instruments Incorporated...
Page 367 1010 COMP3OUT input Values not shown are reserved. If a device does not have a particular comparator, then that option is reserved. SPRUH18I – JANUARY 2011 – REVISED JUNE 2022 TMS320x2806x Microcontrollers Submit Document Feedback Copyright © 2022 Texas Instruments Incorporated...
Page 368 1010 COMP3OUT input Values not shown are reserved. If a device does not have a particular comparator, then that option is reserved. TMS320x2806x Microcontrollers SPRUH18I – JANUARY 2011 – REVISED JUNE 2022 Submit Document Feedback Copyright © 2022 Texas Instruments Incorporated...
Page 369 Source Is Synchronous Signal Source Is Asynchronous Signal EVT1SRCSEL DCAEVT1 Source Signal Select Source Is DCAEVT1 Signal Source Is DCEVTFILT Signal SPRUH18I – JANUARY 2011 – REVISED JUNE 2022 TMS320x2806x Microcontrollers Submit Document Feedback Copyright © 2022 Texas Instruments Incorporated...
Page 370 Source Is Synchronous Signal Source Is Asynchronous Signal EVT1SRCSEL DCBEVT1 Source Signal Select Source Is DCBEVT1 Signal Source Is DCEVTFILT Signal TMS320x2806x Microcontrollers SPRUH18I – JANUARY 2011 – REVISED JUNE 2022 Submit Document Feedback Copyright © 2022 Texas Instruments Incorporated...
Page 371 Filter Block Signal Source Select Source Is DCAEVT1 Signal Source Is DCAEVT2 Signal Source Is DCBEVT1 Signal Source Is DCBEVT2 Signal SPRUH18I – JANUARY 2011 – REVISED JUNE 2022 TMS320x2806x Microcontrollers Submit Document Feedback Copyright © 2022 Texas Instruments Incorporated...
Page 372 CAPE TBCTR Counter Capture Enable/Disable Disable the time-base counter capture. Enable the time-base counter capture. TMS320x2806x Microcontrollers SPRUH18I – JANUARY 2011 – REVISED JUNE 2022 Submit Document Feedback Copyright © 2022 Texas Instruments Incorporated...
Page 373 The offset counter is not affected by the free/soft emulation bits. That is, it will always continue to count down if the device is halted by a emulation stop. SPRUH18I – JANUARY 2011 – REVISED JUNE 2022 TMS320x2806x Microcontrollers Submit Document Feedback Copyright © 2022 Texas Instruments Incorporated...
Page 374 These 8 bits are read only and indicate the current value of the window counter. The counter counts down to zero and then stops until it is re-loaded when the offset counter reaches zero again. TMS320x2806x Microcontrollers SPRUH18I – JANUARY 2011 – REVISED JUNE 2022 Submit Document Feedback Copyright © 2022 Texas Instruments Incorporated...
Page 375 4. Initialize peripheral registers 5. Set TBCLKSYNC=1 6. Clear any spurious ePWM flags (including PIEIFR) 7. Enable ePWM interrupts 8. Enable global interrupts SPRUH18I – JANUARY 2011 – REVISED JUNE 2022 TMS320x2806x Microcontrollers Submit Document Feedback Copyright © 2022 Texas Instruments Incorporated...
Page 376 Enhanced Pulse Width Modulator (ePWM) Module www.ti.com This page intentionally left blank. TMS320x2806x Microcontrollers SPRUH18I – JANUARY 2011 – REVISED JUNE 2022 Submit Document Feedback Copyright © 2022 Texas Instruments Incorporated...
Page 377 The ePWMxB output will have a ±1-2 cycle jitter in this mode. Introduction................................378 4.2 Operational Description of HRPWM........................379 4.3 SFO Library Software - SFO_TI_Build_V6.lib......................4.4 HRPWM Registers..............................SPRUH18I – JANUARY 2011 – REVISED JUNE 2022 TMS320x2806x Microcontrollers Submit Document Feedback Copyright © 2022 Texas Instruments Incorporated...
Page 378 Single-phase buck, boost, and flyback • Multi-phase buck, boost, and flyback • Phase-shifted full bridge • Direct modulation of D-Class power amplifiers TMS320x2806x Microcontrollers SPRUH18I – JANUARY 2011 – REVISED JUNE 2022 Submit Document Feedback Copyright © 2022 Texas Instruments Incorporated...
Page 379 High Resolution Period Control Register TBPRDHRM 0x002A Extension Mirror Register for HRPWM Period (8 bits) CMPAHRM 0x002C Extension Mirror Register for HRPWM Duty (8 bits) SPRUH18I – JANUARY 2011 – REVISED JUNE 2022 TMS320x2806x Microcontrollers Submit Document Feedback Copyright © 2022 Texas Instruments Incorporated...
Page 380 B signal path is available by properly configuring the HRCNFG register. Figure 4-4 shows how the HRPWM interfaces with the 8-bit extension registers. TMS320x2806x Microcontrollers SPRUH18I – JANUARY 2011 – REVISED JUNE 2022 Submit Document Feedback Copyright © 2022 Texas Instruments Incorporated...
Page 381 These events are generated by the type 1 ePWM digital compare (DC) submodule based on the levels of the COMPxOUT and TZ signals. Figure 4-4. HRPWM System Interface SPRUH18I – JANUARY 2011 – REVISED JUNE 2022 TMS320x2806x Microcontrollers Submit Document Feedback Copyright © 2022 Texas Instruments Incorporated...
Page 382 (PC) (TZ) EPWMB EPWMxBO 1. From ePWM time-base (TB) submodule. 2. From ePWM counter-compare (CC) submodule. Figure 4-5. HRPWM Block Diagram TMS320x2806x Microcontrollers SPRUH18I – JANUARY 2011 – REVISED JUNE 2022 Submit Document Feedback Copyright © 2022 Texas Instruments Incorporated...
Page 383 Auto-conversion for high-resolution period has the same behavior as auto-conversion for high-resolution duty cycle. Auto-conversion must always be enabled for high-resolution period mode. SPRUH18I – JANUARY 2011 – REVISED JUNE 2022 TMS320x2806x Microcontrollers Submit Document Feedback Copyright © 2022 Texas Instruments Incorporated...
Page 384 19 20 21 22 23 EPWM1A 26.3% 29.2% 31.9% 27.8% 30.6% Figure 4-6. Required PWM Waveform for a Requested Duty = 30.0% TMS320x2806x Microcontrollers SPRUH18I – JANUARY 2011 – REVISED JUNE 2022 Submit Document Feedback Copyright © 2022 Texas Instruments Incorporated...
Page 385 ≥ 0.5, this rounding constant will round the CMPAHR value up 1 MEP step. = 0.5 (0 080h in Q8 format) SPRUH18I – JANUARY 2011 – REVISED JUNE 2022 TMS320x2806x Microcontrollers Submit Document Feedback Copyright © 2022 Texas Instruments Incorporated...
Page 386 (11 SYSCLKOUT cycles ) that takes a Q15 duty value as input and writes a single [CMPA:CMPAHR] value. TMS320x2806x Microcontrollers SPRUH18I – JANUARY 2011 – REVISED JUNE 2022 Submit Document Feedback Copyright © 2022 Texas Instruments Incorporated...
Page 387 This limitation applies only if high-resolution period (TBPRDHR) control is enabled. SYSCLKOUT = TBCLK TBPRD EPWM1A Figure 4-7. Low % Duty Cycle Range Limitation Example (HRPCTL[HRPE] = 0) SPRUH18I – JANUARY 2011 – REVISED JUNE 2022 TMS320x2806x Microcontrollers Submit Document Feedback Copyright © 2022 Texas Instruments Incorporated...
Page 388 Figure 4-8. High % Duty Cycle Range Limitation Example (HRPCTL[HRPE] = 0) SYSCLKOUT= TBCLK TBPRD - 3 TBPRD EPWM1A Figure 4-9. Up-Count Duty Cycle Range Limitation Example (HRPCTL[HRPE]=1) TMS320x2806x Microcontrollers SPRUH18I – JANUARY 2011 – REVISED JUNE 2022 Submit Document Feedback Copyright © 2022 Texas Instruments Incorporated...
Page 389 Number of MEP steps per coarse step at 180 ps (MEP_ScaleFactor) = 61 (11.1 ns/180 ps) Value to keep TBPRDHR within range of 1-255 and fractional = 0.5 (0080h in Q8 format) rounding constant (default value) SPRUH18I – JANUARY 2011 – REVISED JUNE 2022 TMS320x2806x Microcontrollers Submit Document Feedback Copyright © 2022 Texas Instruments Incorporated...
Page 390 TBPRDHR MEP delay is scaled by hardware to: = (0049h × 61 + 80h) >> 8 =(11E5h) >> 8 Period MEP delay =0011h MEP Steps TMS320x2806x Microcontrollers SPRUH18I – JANUARY 2011 – REVISED JUNE 2022 Submit Document Feedback Copyright © 2022 Texas Instruments Incorporated...
Page 391 PWM is running, the jitter will appear on the PWM output at the time of the sync pulse. SPRUH18I – JANUARY 2011 – REVISED JUNE 2022 TMS320x2806x Microcontrollers Submit Document Feedback Copyright © 2022 Texas Instruments Incorporated...
Page 392 #define HR_CTR_ZERO_PRD 0x2 // CTR = ZERO or Period event #define HR_NORM_B // Normal ePWMxB output #define HR_INVERT_B 0x1 // ePWMxB is inverted ePWMxA output TMS320x2806x Microcontrollers SPRUH18I – JANUARY 2011 – REVISED JUNE 2022 Submit Document Feedback Copyright © 2022 Texas Instruments Incorporated...
Page 393 The example code shown consists of two main parts: • Initialization code (executed once) • Run time code (typically executed within an ISR) SPRUH18I – JANUARY 2011 – REVISED JUNE 2022 TMS320x2806x Microcontrollers Submit Document Feedback Copyright © 2022 Texas Instruments Incorporated...
Page 394 ; CMPA:CMPAHR(31:8) <= ACC ; Output for EPWM1B (Regular Res) Optional - for comparison purpose only MOV *+XAR3[2],AH ; Store ACCH to regular CMPB TMS320x2806x Microcontrollers SPRUH18I – JANUARY 2011 – REVISED JUNE 2022 Submit Document Feedback Copyright © 2022 Texas Instruments Incorporated...
Page 395 Run time code (typically executed within an ISR) This example assumes a typical MEP_SP and does not use the SFO library. SPRUH18I – JANUARY 2011 – REVISED JUNE 2022 TMS320x2806x Microcontrollers Submit Document Feedback Copyright © 2022 Texas Instruments Incorporated...
Page 396 ; CMPA:CMPAHR(31:8) <= ACC ; Output for EPWM1B (Regular Res) Optional - for comparison purpose only MOV *+XAR3[2],AH ; Store ACCH to regular CMPB TMS320x2806x Microcontrollers SPRUH18I – JANUARY 2011 – REVISED JUNE 2022 Submit Document Feedback Copyright © 2022 Texas Instruments Incorporated...
Page 397 SFO_TI_Build_V6.lib, the SFO() function does not automatically update the HRMSTEP register. Therefore, after the SFO function completes, the application software must write MEP_ScaleFactor to the HRMSTEP register (EALLOW-protected). SPRUH18I – JANUARY 2011 – REVISED JUNE 2022 TMS320x2806x Microcontrollers Submit Document Feedback Copyright © 2022 Texas Instruments Incorporated...
Page 398 Example 4-6. A Sample of How to Add "Include" Files #include "F2806x_Device.h" // F2806x Headerfile #include "F2806x_EPwm_defines.h" // init defines #include "SFO_V6.h" // SFO lib functions (needed for HRPWM) TMS320x2806x Microcontrollers SPRUH18I – JANUARY 2011 – REVISED JUNE 2022 Submit Document Feedback Copyright © 2022 Texas Instruments Incorporated...
Page 399 = SFO(); if(status==2) {ESTOP0;} // The function returns a 2 if MEP_ScaleFactor is greater // than the maximum 255 allowed (error condition) SPRUH18I – JANUARY 2011 – REVISED JUNE 2022 TMS320x2806x Microcontrollers Submit Document Feedback Copyright © 2022 Texas Instruments Incorporated...
Page 400 = SFO_INCOMPLETE; while (status==SFO_INCOMPLETE) { status = SFO(); if(status!=SFO_ERROR) { // IF SFO() is complete with no errors EALLOW; EPwm1Regs.HRMSTEP=MEP_ScaleFactor; EDIS; TMS320x2806x Microcontrollers SPRUH18I – JANUARY 2011 – REVISED JUNE 2022 Submit Document Feedback Copyright © 2022 Texas Instruments Incorporated...
Page 401 CTLMODE EDGMODE R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 LEGEND: R/W = Read/Write; R = Read only; -n = value after reset SPRUH18I – JANUARY 2011 – REVISED JUNE 2022 TMS320x2806x Microcontrollers Submit Document Feedback Copyright © 2022 Texas Instruments Incorporated...
Page 402 Figure 4-16. High Resolution Micro Step (HRMSTEP) Register Reserved HRMSTEP R/W-0 LEGEND: R/W = Read/Write; R = Read only; -n = value after reset TMS320x2806x Microcontrollers SPRUH18I – JANUARY 2011 – REVISED JUNE 2022 Submit Document Feedback Copyright © 2022 Texas Instruments Incorporated...
Page 403 The value in this register is written by the SFO calibration software at the end of each calibration run. This register is EALLOW protected. SPRUH18I – JANUARY 2011 – REVISED JUNE 2022 TMS320x2806x Microcontrollers Submit Document Feedback Copyright © 2022 Texas Instruments Incorporated...
Page 404 When high-resolution period is enabled, TBCTL[CTRMODE] = 0,1 (down-count mode) is not supported. This register is EALLOW protected. This register is used with Type 1 ePWM modules (support high-resolution period) only. TMS320x2806x Microcontrollers SPRUH18I – JANUARY 2011 – REVISED JUNE 2022 Submit Document Feedback Copyright © 2022 Texas Instruments Incorporated...
Page 405 HRCAP module of the same type, to determine the differences between types, and for a list of device-specific differences within a type. Introduction................................406 Description................................406 5.3 Operational Details..............................407 5.4 HRCAP Calibration Library............................413 5.5 HRCAP Register Descriptions..........................421 SPRUH18I – JANUARY 2011 – REVISED JUNE 2022 TMS320x2806x Microcontrollers Submit Document Feedback Copyright © 2022 Texas Instruments Incorporated...
Page 406 HRPWM instances, ePWM8A HRPWM output is the internal HRCAP calibration signal input. Figure 5-1. HRCAP Module System Block Diagram TMS320x2806x Microcontrollers SPRUH18I – JANUARY 2011 – REVISED JUNE 2022 Submit Document Feedback Copyright © 2022 Texas Instruments Incorporated...
Page 407 SYSCLK2. On this device, HCCAPCLK is clocked by SYSCLKOUT or PLL2. Figure 5-3 shows how the HCCAPCLK that clocks the HCCOUNTER and edge detection logic is generated. SPRUH18I – JANUARY 2011 – REVISED JUNE 2022 TMS320x2806x Microcontrollers Submit Document Feedback Copyright © 2022 Texas Instruments Incorporated...
Page 408 HCCAPCLK HRCAPx HCCOUNTER 0x0000 0x0001 0x0002 0x0003 0x0004 0x0000 HCCAPCNTFALL0 + 1 Figure 5-4. HCCOUNTER Behavior During High Pulse Width Capture TMS320x2806x Microcontrollers SPRUH18I – JANUARY 2011 – REVISED JUNE 2022 Submit Document Feedback Copyright © 2022 Texas Instruments Incorporated...
Page 409 After the second rise interrupt, all capture data is valid and can be used normally. SPRUH18I – JANUARY 2011 – REVISED JUNE 2022 TMS320x2806x Microcontrollers Submit Document Feedback Copyright © 2022 Texas Instruments Incorporated...
Page 410 In both cases, 1 is added to the value in the HCCAPCNT registers to account for the HCCAPCLK cycle in which HCCOUNTER = 0. TMS320x2806x Microcontrollers SPRUH18I – JANUARY 2011 – REVISED JUNE 2022 Submit Document Feedback Copyright © 2022 Texas Instruments Incorporated...
Page 411 HRCAP calibration input must be dedicated only to calibration and cannot be used functionally in the application during calibration. Texas Instruments provides a calibration function in the HCCal HRCAP calibration library to perform this calibration once prior to using the HRCAP in high-resolution capture mode and periodically in a slow loop to account for changes in the HRCAP step size due to voltage and temperature changes while the application is running.
Page 412 Input = 1 FALL Capture HCCTL[FALLINTE] Interrupt Event HCIFR[OVF] clear HCICLR[OVF] Latch HCIFRC[OVF] Counter Overflow HCCTL[OVFINTE] Event Figure 5-9. Interrupts in HRCAP Module TMS320x2806x Microcontrollers SPRUH18I – JANUARY 2011 – REVISED JUNE 2022 Submit Document Feedback Copyright © 2022 Texas Instruments Incorporated...
Page 413 HCCAPCLK cycles based on the values in the HCCAPCNT registers and the calibration results. The contents of these functions are proprietary to Texas Instruments and will not be published. Currently, there is 1 released version of the HCCal Type 0 library, HCCal_Type0_V1.lib, which is located in the C2000ware software package under the \libraries\calibration\hrcap\ directory.
Page 414 For instance, on this device, while the HRCAP is in use in high-resolution capture mode, ePWM8 cannot be used functionally by the application during calibration. TMS320x2806x Microcontrollers SPRUH18I – JANUARY 2011 – REVISED JUNE 2022 Submit Document Feedback Copyright © 2022 Texas Instruments Incorporated...
Page 415 Service RISE interrupt LowPulseWidth0 HCCAPCNTRISE1 HCCAPCNTFALL1 HCCAPCNTRISE0 Service FALL interrupt LowPulseWidth0 HCCAPCNTFALL0 HCCAPCNTFALL1 HCCAPCNTRISE0 Figure 5-10. LowPulseWidth0 Capture on RISE and FALL Events SPRUH18I – JANUARY 2011 – REVISED JUNE 2022 TMS320x2806x Microcontrollers Submit Document Feedback Copyright © 2022 Texas Instruments Incorporated...
Page 416 Service RISE interrupt HCCAPCNTRISE1 HCCAPCNTFALL1 HCCAPCNTRISE0 HighPulseWidth1 HCCAPCNTFALL1 HCCAPCNTRISE0 HCCAPCNTFALL0 HighPulseWidth0 HighPulseWidth1 Figure 5-11. HighPulseWidth0/1 Capture on RISE and FALL Events TMS320x2806x Microcontrollers SPRUH18I – JANUARY 2011 – REVISED JUNE 2022 Submit Document Feedback Copyright © 2022 Texas Instruments Incorporated...
Page 417 Q16 integer + fractional high-resolution period width in HCCAPCLK cycles. Figure 5-12 shows which period widths can be captured on a RISE and FALL event. SPRUH18I – JANUARY 2011 – REVISED JUNE 2022 TMS320x2806x Microcontrollers Submit Document Feedback Copyright © 2022 Texas Instruments Incorporated...
Page 418 PeriodWidthRise0 Service FALL interrupt HCCAPCNTRISE1 HCCAPCNTFALL1 HCCAPCNTRISE0 HCCAPCNTFALL0 PeriodWidthRise0 PeriodWidthFall0 Figure 5-12. PeriodWidthRise0 and PeriodWidthFall0 Capture on RISE and FALL Events TMS320x2806x Microcontrollers SPRUH18I – JANUARY 2011 – REVISED JUNE 2022 Submit Document Feedback Copyright © 2022 Texas Instruments Incorporated...
Page 419 // ePWM8A = HRCAP calibration input status = HRCAP_Cal(2,HCCAPCLK_PLLCLK, &EPwm8Regs); if (status == HCCAL_ERROR) ESTOP0; // Error, stop and check HCCAPCLK frequency SPRUH18I – JANUARY 2011 – REVISED JUNE 2022 TMS320x2806x Microcontrollers Submit Document Feedback Copyright © 2022 Texas Instruments Incorporated...
Page 420 // clock start to edge - invalid pulse width) } else { periodwidth = PeriodWidthRise0((Uint16 *)&HRCap1Regs); pulsewidthlow = LowPulseWidth0((Uint16 *)&HRCap1Regs); pulsewidthhigh = HighPulseWidth0((Uint16 *)&HRCap1Regs); HRCap1Regs.HCICLR.bit.RISE=1; HRCap1Regs.HCICLR.bit.INT=1; PieCtrlRegs.PIEACK.bit.ACK4=1; EDIS; TMS320x2806x Microcontrollers SPRUH18I – JANUARY 2011 – REVISED JUNE 2022 Submit Document Feedback Copyright © 2022 Texas Instruments Incorporated...
Page 421 HRCAP Capture Counter On Rising Edge 1 Register Section 5.5.8 HCCAPCNTFALL1 0x1A HRCAP Capture Counter On Falling Edge 1 Register Section 5.5.9 SPRUH18I – JANUARY 2011 – REVISED JUNE 2022 TMS320x2806x Microcontrollers Submit Document Feedback Copyright © 2022 Texas Instruments Incorporated...
Page 422 Writes of "1" to this bit will clear HCCOUNTER, all capture registers, and the IFR register bits. This register is EALLOW protected. TMS320x2806x Microcontrollers SPRUH18I – JANUARY 2011 – REVISED JUNE 2022 Submit Document Feedback Copyright © 2022 Texas Instruments Incorporated...
Page 423 An enabled RISE, FALL or COUNTEROVF interrupt has been generated. No further interrupts are generated until this bit is cleared. This register is EALLOW protected. SPRUH18I – JANUARY 2011 – REVISED JUNE 2022 TMS320x2806x Microcontrollers Submit Document Feedback Copyright © 2022 Texas Instruments Incorporated...
Page 424 HCIFR[INT] flag bit has priority over the software clear if both happen on the same cycle. This register is EALLOW protected. TMS320x2806x Microcontrollers SPRUH18I – JANUARY 2011 – REVISED JUNE 2022 Submit Document Feedback Copyright © 2022 Texas Instruments Incorporated...
Page 425 HCCTL[SOFTRESET] clearing of the HCIFR[RISE] bit has priority over the hardware trying to set the bit in the same cycle. Reserved Reserved This register is EALLOW protected. SPRUH18I – JANUARY 2011 – REVISED JUNE 2022 TMS320x2806x Microcontrollers Submit Document Feedback Copyright © 2022 Texas Instruments Incorporated...
Page 426 CPU reads to this register should not be performed unless the clocks to the HRCAP module are disabled (HRCAPxENCLK = 0). TMS320x2806x Microcontrollers SPRUH18I – JANUARY 2011 – REVISED JUNE 2022 Submit Document Feedback Copyright © 2022 Texas Instruments Incorporated...
Page 427 HRCAP capture counter on falling edge 0 register This register captures the16-bit HCCOUNTER value when a Falling edge event is detected. SPRUH18I – JANUARY 2011 – REVISED JUNE 2022 TMS320x2806x Microcontrollers Submit Document Feedback Copyright © 2022 Texas Instruments Incorporated...
Page 428 On an input falling edge event, the value in the HCCAPCNTFALL0 register is copied into the HCCAPCNTFALL1 register before the HCCOUNTER value is captured into the HCCAPCNTFALL0 register. TMS320x2806x Microcontrollers SPRUH18I – JANUARY 2011 – REVISED JUNE 2022 Submit Document Feedback Copyright © 2022 Texas Instruments Incorporated...
Page 429 6.3 Capture and APWM Operating Mode........................432 6.4 Capture Mode Description............................434 6.5 Application of the eCAP Module..........................6.6 Application of the APWM Mode..........................446 6.7 eCAP Registers.................................446 SPRUH18I – JANUARY 2011 – REVISED JUNE 2022 TMS320x2806x Microcontrollers Submit Document Feedback Copyright © 2022 Texas Instruments Incorporated...
Page 430 Multiple identical eCAP modules can be contained in a system as shown in Figure 6-1. The number of modules is device-dependent and is based on target application needs. TMS320x2806x Microcontrollers SPRUH18I – JANUARY 2011 – REVISED JUNE 2022 Submit Document Feedback Copyright © 2022 Texas Instruments Incorporated...
Page 431 APWM2 GPIO module ECAP2INT SyncOut SyncIn ECAPx/ ECAPx APWMx module ECAPxINT SyncOut Figure 6-1. Multiple eCAP Modules In A C28x System SPRUH18I – JANUARY 2011 – REVISED JUNE 2022 TMS320x2806x Microcontrollers Submit Document Feedback Copyright © 2022 Texas Instruments Incorporated...
Page 432 CAP3/CAP4. This emulates immediate mode. Writing to the shadow registers CAP3/CAP4 invokes the shadow mode. Figure 6-2. Capture and APWM Modes of Operation TMS320x2806x Microcontrollers SPRUH18I – JANUARY 2011 – REVISED JUNE 2022 Submit Document Feedback Copyright © 2022 Texas Instruments Incorporated...
Page 433 CMP [0-31] 0000000C ECAPOUT Off−time Period time Figure 6-3. Counter Compare and PRD Effects on the eCAP Output in APWM Mode SPRUH18I – JANUARY 2011 – REVISED JUNE 2022 TMS320x2806x Microcontrollers Submit Document Feedback Copyright © 2022 Texas Instruments Incorporated...
Page 434 Capture Control Flag CTR=PRD control CTR=CMP ECCTL2 [ RE−ARM, CONT/ONESHT, STOP_WRAP] Registers: ECEINT, ECFLG, ECCLR, ECFRC Figure 6-4. eCAP Block Diagram TMS320x2806x Microcontrollers SPRUH18I – JANUARY 2011 – REVISED JUNE 2022 Submit Document Feedback Copyright © 2022 Texas Instruments Incorporated...
Page 435 ECAPx PSout div 2 PSout div 4 PSout div 6 PSout div 8 PSout div 10 Figure 6-6. Prescale Function Waveforms SPRUH18I – JANUARY 2011 – REVISED JUNE 2022 TMS320x2806x Microcontrollers Submit Document Feedback Copyright © 2022 Texas Instruments Incorporated...
Page 436 CEVT3 Stop counter CEVT4 Mod_eq One−shot control logic Stop value (2b) ECCTL2[STOP_WRAP] ECCTL2[RE−ARM] ECCTL2[CONT/ONESHT] Figure 6-7. Details of the Continuous/One-shot Block TMS320x2806x Microcontrollers SPRUH18I – JANUARY 2011 – REVISED JUNE 2022 Submit Document Feedback Copyright © 2022 Texas Instruments Incorporated...
Page 437 CAP1 and CAP2 registers become the active period and compare registers, respectively, in APWM mode. CAP3 and CAP4 registers become the respective shadow registers (APRD and ACMP) for CAP1 and CAP2 during APWM operation. SPRUH18I – JANUARY 2011 – REVISED JUNE 2022 TMS320x2806x Microcontrollers Submit Document Feedback Copyright © 2022 Texas Instruments Incorporated...
Page 438 == 0]). The CTR=PRD, CTR=CMP flags are only valid in APWM mode (ECCTL2[CAP/APWM == 1]). CNTOVF flag is valid in both modes. TMS320x2806x Microcontrollers SPRUH18I – JANUARY 2011 – REVISED JUNE 2022 Submit Document Feedback Copyright © 2022 Texas Instruments Incorporated...
Page 439 DMA. Any one of the four available interrupt events () can be selected as the trigger source for ECAP_DMA_INT using ECCTL2 [DMAEVTSEL]. SPRUH18I – JANUARY 2011 – REVISED JUNE 2022 TMS320x2806x Microcontrollers Submit Document Feedback Copyright © 2022 Texas Instruments Incorporated...
Page 440 1000h APRD 500h ACMP 300h 0000000C APWMx (o/p pin) Off−time Period time Figure 6-10. PWM Waveform Details Of APWM Mode Operation TMS320x2806x Microcontrollers SPRUH18I – JANUARY 2011 – REVISED JUNE 2022 Submit Document Feedback Copyright © 2022 Texas Instruments Incorporated...
Page 441 CMP = PERIOD+1, output low for complete period (100% duty) CMP > PERIOD+1, output low for complete period CAP1 1 TSCTR Figure 6-11. Time-Base Frequency and Period Calculation SPRUH18I – JANUARY 2011 – REVISED JUNE 2022 TMS320x2806x Microcontrollers Submit Document Feedback Copyright © 2022 Texas Instruments Incorporated...
Page 442 Polarity selection (can be read) at this time Capture registers [1−4] Figure 6-12. Capture Sequence for Absolute Time-stamp and Rising Edge Detect TMS320x2806x Microcontrollers SPRUH18I – JANUARY 2011 – REVISED JUNE 2022 Submit Document Feedback Copyright © 2022 Texas Instruments Incorporated...
Page 443 CAP2 CAP3 CAP4 Polarity selection Capture registers [1−4] Figure 6-13. Capture Sequence for Absolute Time-stamp With Rising and Falling Edge Detect SPRUH18I – JANUARY 2011 – REVISED JUNE 2022 TMS320x2806x Microcontrollers Submit Document Feedback Copyright © 2022 Texas Instruments Incorporated...
Page 444 All capture values valid (can be read) at this time Figure 6-14. Capture Sequence for Delta Mode Time-stamp and Rising Edge Detect TMS320x2806x Microcontrollers SPRUH18I – JANUARY 2011 – REVISED JUNE 2022 Submit Document Feedback Copyright © 2022 Texas Instruments Incorporated...
Page 445 CAP3 CAP4 Polarity selection Capture registers [1−4] Figure 6-15. Capture Sequence for Delta Mode Time-stamp With Rising and Falling Edge Detect SPRUH18I – JANUARY 2011 – REVISED JUNE 2022 TMS320x2806x Microcontrollers Submit Document Feedback Copyright © 2022 Texas Instruments Incorporated...
Page 446 Table 6-1. ECAP Base Address Table Bit Field Name Base Address Instance Structure ECap1Regs ECAP_REGS 0x0000_6A00 ECap2Regs ECAP_REGS 0x0000_6A20 ECap3Regs ECAP_REGS 0x0000_6A40 TMS320x2806x Microcontrollers SPRUH18I – JANUARY 2011 – REVISED JUNE 2022 Submit Document Feedback Copyright © 2022 Texas Instruments Incorporated...
Page 447 When this variable is used in a register name, an offset, or an address it refers to the value of a register array. SPRUH18I – JANUARY 2011 – REVISED JUNE 2022 TMS320x2806x Microcontrollers Submit Document Feedback Copyright © 2022 Texas Instruments Incorporated...
Page 448 SYNCI event or S/W force via a control bit. Used to achieve phase control synchronization with respect to other eCAP and EPWM timebases. Reset type: SYSRSn TMS320x2806x Microcontrollers SPRUH18I – JANUARY 2011 – REVISED JUNE 2022 Submit Document Feedback Copyright © 2022 Texas Instruments Incorporated...
Page 449 - Software - may be useful for test purposes - ACMP shadow register (CAP4) when used in APWM mode Reset type: SYSRSn SPRUH18I – JANUARY 2011 – REVISED JUNE 2022 TMS320x2806x Microcontrollers Submit Document Feedback Copyright © 2022 Texas Instruments Incorporated...
Page 450 In APWM mode, this is the compare shadow (ACMP) register. You can update the PWM compare value via this register. CAP4 (ACMP) shadows CAP2 in this mode. Reset type: SYSRSn TMS320x2806x Microcontrollers SPRUH18I – JANUARY 2011 – REVISED JUNE 2022 Submit Document Feedback Copyright © 2022 Texas Instruments Incorporated...
Page 451 0h (R/W) = Capture Event 4 triggered on a rising edge (RE) 1h (R/W) = Capture Event 4 triggered on a falling edge (FE) SPRUH18I – JANUARY 2011 – REVISED JUNE 2022 TMS320x2806x Microcontrollers Submit Document Feedback Copyright © 2022 Texas Instruments Incorporated...
Page 452 0h (R/W) = Capture Event 1 triggered on a rising edge (RE) 1h (R/W) = Capture Event 1 triggered on a falling edge (FE) TMS320x2806x Microcontrollers SPRUH18I – JANUARY 2011 – REVISED JUNE 2022 Submit Document Feedback Copyright © 2022 Texas Instruments Incorporated...
Page 453 Note: Selection CTR = PRD is meaningful only in APWM mode however, you can choose it in CAP mode if you find doing so useful. SPRUH18I – JANUARY 2011 – REVISED JUNE 2022 TMS320x2806x Microcontrollers Submit Document Feedback Copyright © 2022 Texas Instruments Incorporated...
Page 454 Continuous or one-shot mode control (applicable only in capture mode) Reset type: SYSRSn 0h (R/W) = Operate in continuous mode 1h (R/W) = Operate in one-Shot mode TMS320x2806x Microcontrollers SPRUH18I – JANUARY 2011 – REVISED JUNE 2022 Submit Document Feedback Copyright © 2022 Texas Instruments Incorporated...
Page 455 0h (R/W) = Disable Capture Event 3 as an Interrupt source 1h (R/W) = Enable Capture Event 3 as an Interrupt source SPRUH18I – JANUARY 2011 – REVISED JUNE 2022 TMS320x2806x Microcontrollers Submit Document Feedback Copyright © 2022 Texas Instruments Incorporated...
Page 456 0h (R/W) = Disable Capture Event 1 as an Interrupt source 1h (R/W) = Enable Capture Event 1 as an Interrupt source RESERVED Reserved TMS320x2806x Microcontrollers SPRUH18I – JANUARY 2011 – REVISED JUNE 2022 Submit Document Feedback Copyright © 2022 Texas Instruments Incorporated...
Page 457 Reset type: SYSRSn 0h (R/W) = Indicates no event occurred 1h (R/W) = Indicates the first event occurred at ECAPx pin. SPRUH18I – JANUARY 2011 – REVISED JUNE 2022 TMS320x2806x Microcontrollers Submit Document Feedback Copyright © 2022 Texas Instruments Incorporated...
Page 458 Global Interrupt Status Flag Reset type: SYSRSn 0h (R/W) = Indicates no event occurred 1h (R/W) = Indicates that an interrupt was generated. TMS320x2806x Microcontrollers SPRUH18I – JANUARY 2011 – REVISED JUNE 2022 Submit Document Feedback Copyright © 2022 Texas Instruments Incorporated...
Page 459 1h (R/W) = Writing a 1 clears the INT flag and enable further interrupts to be generated if any of the event flags are set to 1 SPRUH18I – JANUARY 2011 – REVISED JUNE 2022 TMS320x2806x Microcontrollers Submit Document Feedback Copyright © 2022 Texas Instruments Incorporated...
Page 460 Reset type: SYSRSn 0h (R/W) = No effect. Always reads back a 0. 1h (R/W) = Sets the CEVT1 flag. RESERVED Reserved TMS320x2806x Microcontrollers SPRUH18I – JANUARY 2011 – REVISED JUNE 2022 Submit Document Feedback Copyright © 2022 Texas Instruments Incorporated...
Page 461 (PCCU)......................471 7.6 eQEP Edge Capture Unit............................478 7.7 eQEP Watchdog................................482 7.8 eQEP Unit Timer Base..............................482 7.9 eQEP Interrupt Structure............................7.10 eQEP Registers...............................483 SPRUH18I – JANUARY 2011 – REVISED JUNE 2022 TMS320x2806x Microcontrollers Submit Document Feedback Copyright © 2022 Texas Instruments Incorporated...
Page 462 QEPA and QEPB outputs varies proportionally with the velocity of the motor. For example, a 2000-line encoder directly coupled to a motor running at 5000 revolutions per minute (rpm) results in a frequency of 166.6 kHz, so TMS320x2806x Microcontrollers SPRUH18I – JANUARY 2011 – REVISED JUNE 2022 Submit Document Feedback Copyright © 2022 Texas Instruments Incorporated...
Page 463 Unit time is basically the inverse of the velocity calculation rate. SPRUH18I – JANUARY 2011 – REVISED JUNE 2022 TMS320x2806x Microcontrollers Submit Document Feedback Copyright © 2022 Texas Instruments Incorporated...
Page 464 The internal pullups can be configured in the GPyPUD register. See the GPIO chapter for more details on GPIO mux and settings. TMS320x2806x Microcontrollers SPRUH18I – JANUARY 2011 – REVISED JUNE 2022 Submit Document Feedback Copyright © 2022 Texas Instruments Incorporated...
Page 465 This signal is typically connected to a sensor or limit switch to notify that the motor has reached a defined position. SPRUH18I – JANUARY 2011 – REVISED JUNE 2022 TMS320x2806x Microcontrollers Submit Document Feedback Copyright © 2022 Texas Instruments Incorporated...
Page 466 QPOSCNT QEINT QPOSCMP QPOSINIT QFRC QPOSMAX QCLR QPOSCTL Enhanced QEP (eQEP) peripheral Figure 7-4. Functional Block Diagram of the eQEP Peripheral TMS320x2806x Microcontrollers SPRUH18I – JANUARY 2011 – REVISED JUNE 2022 Submit Document Feedback Copyright © 2022 Texas Instruments Incorporated...
Page 467 Capture Period Register QCTMRLAT 0x1F 0x0000 eQEP Capture Timer Latch QCPRDLAT 0x20 0x0000 eQEP Capture Period Latch reserved 0x21 31/0 0x3F SPRUH18I – JANUARY 2011 – REVISED JUNE 2022 TMS320x2806x Microcontrollers Submit Document Feedback Copyright © 2022 Texas Instruments Incorporated...
Page 468 Clock and direction input to the position counter is selected using QDECCTL[QSRC] bits, based on interface input requirement as follows: • Quadrature-count mode • Direction-count mode • UP-count mode TMS320x2806x Microcontrollers SPRUH18I – JANUARY 2011 – REVISED JUNE 2022 Submit Document Feedback Copyright © 2022 Texas Instruments Incorporated...
Page 469 Decrement counter counter QEPA QEPB Decrement Decrement counter counter eQEP signals Increment Increment counter counter Figure 7-6. Quadrature Decoder State Machine SPRUH18I – JANUARY 2011 – REVISED JUNE 2022 TMS320x2806x Microcontrollers Submit Document Feedback Copyright © 2022 Texas Instruments Incorporated...
Page 470 The position counter is incremented on every rising edge of a QEPA input when the direction input is high, and decremented when the direction input is low. TMS320x2806x Microcontrollers SPRUH18I – JANUARY 2011 – REVISED JUNE 2022 Submit Document Feedback Copyright © 2022 Texas Instruments Incorporated...
Page 471 Overflow occurs when the position counter counts up after the QPOSMAX value. Underflow occurs when the position counter counts down after "0". The Interrupt flag is set to indicate overflow/underflow in QFLG register. SPRUH18I – JANUARY 2011 – REVISED JUNE 2022 TMS320x2806x Microcontrollers Submit Document Feedback Copyright © 2022 Texas Instruments Incorporated...
Page 472 QCLK edge is less than SYSCLK period, then QPOSCNT gets reset to zero or QPOSMAX in the same SYSCLK cycle and does not wait for the next QCLK edge to occur. TMS320x2806x Microcontrollers SPRUH18I – JANUARY 2011 – REVISED JUNE 2022 Submit Document Feedback Copyright © 2022 Texas Instruments Incorporated...
Page 473 Section 7.5.1.2. The first index marker fields (QEPSTS[FIDF] and QEPSTS[FIMF]) are not applicable in this mode. SPRUH18I – JANUARY 2011 – REVISED JUNE 2022 TMS320x2806x Microcontrollers Submit Document Feedback Copyright © 2022 Texas Instruments Incorporated...
Page 474 (QEPCTL[IEL]=11). Figure 7-10 shows the position counter latch using an index event marker. TMS320x2806x Microcontrollers SPRUH18I – JANUARY 2011 – REVISED JUNE 2022 Submit Document Feedback Copyright © 2022 Texas Instruments Incorporated...
Page 475 The strobe event latch interrupt flag (QFLG[SEL) is set when the position counter is latched to the QPOSSLAT register. QCLK QEPST:QDF QPOSCNT QIPOSSLAT Figure 7-11. Strobe Event Latch (QEPCTL[SEL] = 1) SPRUH18I – JANUARY 2011 – REVISED JUNE 2022 TMS320x2806x Microcontrollers Submit Document Feedback Copyright © 2022 Texas Instruments Incorporated...
Page 476 (QFLG[PCR]) interrupt after loading. • Load on compare match • Load on position-counter zero event TMS320x2806x Microcontrollers SPRUH18I – JANUARY 2011 – REVISED JUNE 2022 Submit Document Feedback Copyright © 2022 Texas Instruments Incorporated...
Page 477 Figure 7-14. QPOSCMP QPOSCNT PCEVNT PCSPW PCSPW PCSPW PCSOUT (active HIGH) Figure 7-14. eQEP Position-compare Sync Output Pulse Stretcher SPRUH18I – JANUARY 2011 – REVISED JUNE 2022 TMS320x2806x Microcontrollers Submit Document Feedback Copyright © 2022 Texas Instruments Incorporated...
Page 478 QPOSLAT, QCTMRLAT and QCPRDLAT registers, respectively, on unit time out. Figure 7-17 shows the capture unit operation along with the position counter. TMS320x2806x Microcontrollers SPRUH18I – JANUARY 2011 – REVISED JUNE 2022 Submit Document Feedback Copyright © 2022 Texas Instruments Incorporated...
Page 479 (such as switching CAPCLK prescaling mode from SYSCLK/4 to SYSCLK/8) only after the capture unit is disabled. SPRUH18I – JANUARY 2011 – REVISED JUNE 2022 TMS320x2806x Microcontrollers Submit Document Feedback Copyright © 2022 Texas Instruments Incorporated...
Page 480 QEPB QCLK x(k) QPOSCNT ∆X x(k−1) UPEVNT t(k) ∆T QCTMR t(k−1) UTOUT Figure 7-17. eQEP Edge Capture Unit - Timing Details TMS320x2806x Microcontrollers SPRUH18I – JANUARY 2011 – REVISED JUNE 2022 Submit Document Feedback Copyright © 2022 Texas Instruments Incorporated...
Page 481 Incremental Position = QPOSLAT(k) - QPOSLAT(K-1) Fixed unit position defined by sensor resolution and ZCAPCTL[UPPS] bits ΔT Capture Period Latch (QCPRDLAT) SPRUH18I – JANUARY 2011 – REVISED JUNE 2022 TMS320x2806x Microcontrollers Submit Document Feedback Copyright © 2022 Texas Instruments Incorporated...
Page 482 Section 7.6. UTIME QEPCTL:UTE SYSCLKOUT QUTMR UTOUT QUPRD QFLG:UTO Figure 7-19. eQEP Unit Timer Base TMS320x2806x Microcontrollers SPRUH18I – JANUARY 2011 – REVISED JUNE 2022 Submit Document Feedback Copyright © 2022 Texas Instruments Incorporated...
Page 483 7.10.1 eQEP Base Addresses Table 7-3. eQEP Base Address Table Bit Field Name Base Address Instance Structure EQep1Regs EQEP_REGS 0x0000_6B00 EQep2Regs EQEP_REGS 0x0000_6B40 SPRUH18I – JANUARY 2011 – REVISED JUNE 2022 TMS320x2806x Microcontrollers Submit Document Feedback Copyright © 2022 Texas Instruments Incorporated...
Page 484 QEP Interrupt Force QEPSTS QEP Status QCTMR QEP Capture Timer QCPRD QEP Capture Period QCTMRLAT QEP Capture Latch QCPRDLAT QEP Capture Period Latch TMS320x2806x Microcontrollers SPRUH18I – JANUARY 2011 – REVISED JUNE 2022 Submit Document Feedback Copyright © 2022 Texas Instruments Incorporated...
Page 485 When this variable is used in a register name, an offset, or an address it refers to the value of a register array. SPRUH18I – JANUARY 2011 – REVISED JUNE 2022 TMS320x2806x Microcontrollers Submit Document Feedback Copyright © 2022 Texas Instruments Incorporated...
Page 486 The position counter can be initialized through software. Writes to this register should always be full 32-bit writes. Reset type: SYSRSn TMS320x2806x Microcontrollers SPRUH18I – JANUARY 2011 – REVISED JUNE 2022 Submit Document Feedback Copyright © 2022 Texas Instruments Incorporated...
Page 487 The position-counter value is latched into this register on an index event as defined by the QEPCTL[IEL] bits. Reset type: SYSRSn SPRUH18I – JANUARY 2011 – REVISED JUNE 2022 TMS320x2806x Microcontrollers Submit Document Feedback Copyright © 2022 Texas Instruments Incorporated...
Page 488 This register acts as time base for unit time event generation. When this timer value matches the unit time period value a unit time event is generated. Reset type: SYSRSn TMS320x2806x Microcontrollers SPRUH18I – JANUARY 2011 – REVISED JUNE 2022 Submit Document Feedback Copyright © 2022 Texas Instruments Incorporated...
Page 489 This register is reset upon edge transition in quadrature-clock indicating the motion. Reset type: SYSRSn SPRUH18I – JANUARY 2011 – REVISED JUNE 2022 TMS320x2806x Microcontrollers Submit Document Feedback Copyright © 2022 Texas Instruments Incorporated...
Page 490 When the watchdog timer value matches the watchdog period value, a watchdog timeout interrupt is generated. Reset type: SYSRSn TMS320x2806x Microcontrollers SPRUH18I – JANUARY 2011 – REVISED JUNE 2022 Submit Document Feedback Copyright © 2022 Texas Instruments Incorporated...
Page 491 1h (R/W) = Negates QEPA input QEPB input polarity Reset type: SYSRSn 0h (R/W) = No effect 1h (R/W) = Negates QEPB input SPRUH18I – JANUARY 2011 – REVISED JUNE 2022 TMS320x2806x Microcontrollers Submit Document Feedback Copyright © 2022 Texas Instruments Incorporated...
Page 492 1h (R/W) = Negates QEPI input QEPS input polarity Reset type: SYSRSn 0h (R/W) = No effect 1h (R/W) = Negates QEPS input RESERVED Reserved TMS320x2806x Microcontrollers SPRUH18I – JANUARY 2011 – REVISED JUNE 2022 Submit Document Feedback Copyright © 2022 Texas Instruments Incorporated...
Page 493 2h (R/W) = Position counter reset on the first index event 3h (R/W) = Position counter reset on a unit time event SPRUH18I – JANUARY 2011 – REVISED JUNE 2022 TMS320x2806x Microcontrollers Submit Document Feedback Copyright © 2022 Texas Instruments Incorporated...
Page 494 QPOSILAT register and the direction flag is latched in the QEPSTS[QDLF] bit. This mode is useful for software index marking. TMS320x2806x Microcontrollers SPRUH18I – JANUARY 2011 – REVISED JUNE 2022 Submit Document Feedback Copyright © 2022 Texas Instruments Incorporated...
Page 495 QEP watchdog enable Reset type: SYSRSn 0h (R/W) = Disable the eQEP watchdog timer 1h (R/W) = Enable the eQEP watchdog timer SPRUH18I – JANUARY 2011 – REVISED JUNE 2022 TMS320x2806x Microcontrollers Submit Document Feedback Copyright © 2022 Texas Instruments Incorporated...
Page 496 Bh (R/W) = UPEVNT = QCLK/2048 Ch (R/W) = Reserved Dh (R/W) = Reserved Eh (R/W) = Reserved Fh (R/W) = Reserved TMS320x2806x Microcontrollers SPRUH18I – JANUARY 2011 – REVISED JUNE 2022 Submit Document Feedback Copyright © 2022 Texas Instruments Incorporated...
Page 497 0h (R/W) = 1 * 4 * SYSCLKOUT cycles 1h (R/W) = 2 * 4 * SYSCLKOUT cycles FFFh (R/W) = 4096 * 4 * SYSCLKOUT cycles SPRUH18I – JANUARY 2011 – REVISED JUNE 2022 TMS320x2806x Microcontrollers Submit Document Feedback Copyright © 2022 Texas Instruments Incorporated...
Page 498 1h (R/W) = Interrupt is enabled Quadrature direction change interrupt enable Reset type: SYSRSn 0h (R/W) = Interrupt is disabled 1h (R/W) = Interrupt is enabled TMS320x2806x Microcontrollers SPRUH18I – JANUARY 2011 – REVISED JUNE 2022 Submit Document Feedback Copyright © 2022 Texas Instruments Incorporated...
Page 499 Position counter error interrupt enable Reset type: SYSRSn 0h (R/W) = Interrupt is disabled 1h (R/W) = Interrupt is enabled RESERVED Reserved SPRUH18I – JANUARY 2011 – REVISED JUNE 2022 TMS320x2806x Microcontrollers Submit Document Feedback Copyright © 2022 Texas Instruments Incorporated...
Page 500 1h (R/W) = Interrupt was generated Quadrature direction change interrupt flag Reset type: SYSRSn 0h (R/W) = No interrupt generated 1h (R/W) = Interrupt was generated TMS320x2806x Microcontrollers SPRUH18I – JANUARY 2011 – REVISED JUNE 2022 Submit Document Feedback Copyright © 2022 Texas Instruments Incorporated...
Page 501 1h (R/W) = Interrupt was generated Global interrupt status flag Reset type: SYSRSn 0h (R/W) = No interrupt generated 1h (R/W) = Interrupt was generated SPRUH18I – JANUARY 2011 – REVISED JUNE 2022 TMS320x2806x Microcontrollers Submit Document Feedback Copyright © 2022 Texas Instruments Incorporated...
Page 502 Clear quadrature direction change interrupt flag Reset type: SYSRSn 0h (R/W) = No effect 1h (R/W) = Clears the interrupt flag TMS320x2806x Microcontrollers SPRUH18I – JANUARY 2011 – REVISED JUNE 2022 Submit Document Feedback Copyright © 2022 Texas Instruments Incorporated...
Page 503 1h (R/W) = Clears the interrupt flag R-0/W1S Global interrupt clear flag Reset type: SYSRSn 0h (R/W) = No effect 1h (R/W) = Clears the interrupt flag SPRUH18I – JANUARY 2011 – REVISED JUNE 2022 TMS320x2806x Microcontrollers Submit Document Feedback Copyright © 2022 Texas Instruments Incorporated...
Page 504 1h (R/W) = Force the interrupt Force quadrature direction change interrupt Reset type: SYSRSn 0h (R/W) = No effect 1h (R/W) = Force the interrupt TMS320x2806x Microcontrollers SPRUH18I – JANUARY 2011 – REVISED JUNE 2022 Submit Document Feedback Copyright © 2022 Texas Instruments Incorporated...
Page 505 Force position counter error interrupt Reset type: SYSRSn 0h (R/W) = No effect 1h (R/W) = Force the interrupt RESERVED Reserved SPRUH18I – JANUARY 2011 – REVISED JUNE 2022 TMS320x2806x Microcontrollers Submit Document Feedback Copyright © 2022 Texas Instruments Incorporated...
Page 506 Reset type: SYSRSn 0h (R/W) = First index pulse has not occurred. 1h (R/W) = Set by first occurrence of index pulse. TMS320x2806x Microcontrollers SPRUH18I – JANUARY 2011 – REVISED JUNE 2022 Submit Document Feedback Copyright © 2022 Texas Instruments Incorporated...
Page 507 Reset Description 15-0 QCPRD This register holds the period count value between the last successive eQEP position events Reset type: SYSRSn SPRUH18I – JANUARY 2011 – REVISED JUNE 2022 TMS320x2806x Microcontrollers Submit Document Feedback Copyright © 2022 Texas Instruments Incorporated...
Page 509 8.8 Power-Up Sequence..............................525 8.9 ADC Calibration................................ 8.10 Internal/External Reference Voltage Selection....................8.11 ADC Timings................................8.12 Internal Temperature Sensor..........................8.13 ADC Registers................................ SPRUH18I – JANUARY 2011 – REVISED JUNE 2022 TMS320x2806x Microcontrollers Submit Document Feedback Copyright © 2022 Texas Instruments Incorporated...
Page 510 TI e2e: Why does the ADC Input Voltage drop with sampling? – Sampling a high impedance voltage divider with ADC • Understanding Data Converters Application Report TMS320x2806x Microcontrollers SPRUH18I – JANUARY 2011 – REVISED JUNE 2022 Submit Document Feedback Copyright © 2022 Texas Instruments Incorporated...
Page 511 TI e2e: ADC Resolution with Oversampling • TI e2e: ADC configuration for interleaved mode • TI e2e: Simultaneous Sampling with Single ADC SPRUH18I – JANUARY 2011 – REVISED JUNE 2022 TMS320x2806x Microcontrollers Submit Document Feedback Copyright © 2022 Texas Instruments Incorporated...
Page 512 ADCINB 6 ADCINB 7 ADCINT1 ADCINT2 ADCCTL1.VREFLOCONV SOC0 – SOC15 SW, ePWM, Configurations Timer, GPIO ADCCTL1.TEMPCONV Figure 8-1. ADC Block Diagram TMS320x2806x Microcontrollers SPRUH18I – JANUARY 2011 – REVISED JUNE 2022 Submit Document Feedback Copyright © 2022 Texas Instruments Incorporated...
Page 513 When configured as such, a single conversion of ADCINA1 will be started on an ePWM3 SOCA event with the resulting value stored in the ADCRESULT0 register. SPRUH18I – JANUARY 2011 – REVISED JUNE 2022 TMS320x2806x Microcontrollers Submit Document Feedback Copyright © 2022 Texas Instruments Incorporated...
Page 514 8-3, the ADCIN pins can be modeled as an RC circuit. With VREFLO connected to ground, a voltage swing from 0 to 3.3 V on ADCIN yields a typical RC time constant of 2 ns. TMS320x2806x Microcontrollers SPRUH18I – JANUARY 2011 – REVISED JUNE 2022 Submit Document Feedback Copyright © 2022 Texas Instruments Incorporated...
Page 515 F ln l OAPPHEJC ANNKN So the total S+H time (t )should be set to at least: = G ® ì SPRUH18I – JANUARY 2011 – REVISED JUNE 2022 TMS320x2806x Microcontrollers Submit Document Feedback Copyright © 2022 Texas Instruments Incorporated...
Page 516 ADC input model, a model of the source impedance/capacitance, and any board parasitics in SPICE (or similar software) and simulate to verify that the sampling capacitor settles to the desired accuracy. TMS320x2806x Microcontrollers SPRUH18I – JANUARY 2011 – REVISED JUNE 2022 Submit Document Feedback Copyright © 2022 Texas Instruments Incorporated...
Page 517 C Table 8-2 shows the relationship between n and the estimated droop error. τ SPRUH18I – JANUARY 2011 – REVISED JUNE 2022 TMS320x2806x Microcontrollers Submit Document Feedback Copyright © 2022 Texas Instruments Incorporated...
Page 518 ADC input model, a model of the source impedance/capacitance, and any board parasitics in SPICE (or similar software) and simulate to verify that the sampling capacitor settles to the desired accuracy. TMS320x2806x Microcontrollers SPRUH18I – JANUARY 2011 – REVISED JUNE 2022 Submit Document Feedback Copyright © 2022 Texas Instruments Incorporated...
Page 519 Sequential mode: Only the next active SOC in RR mode (one up from current RR pointer) will be allowed to generate SOC; all other triggers for other SOC slots will be ignored. SPRUH18I – JANUARY 2011 – REVISED JUNE 2022 TMS320x2806x Microcontrollers Submit Document Feedback Copyright © 2022 Texas Instruments Incorporated...
Page 520 SOC0. The RRPOINTER is reset by a device reset, when the ADCCTL1.RESET bit is set, or when the SOCPRICTL register is written. An example of the round robin priority method is given in Figure 8-5 TMS320x2806x Microcontrollers SPRUH18I – JANUARY 2011 – REVISED JUNE 2022 Submit Document Feedback Copyright © 2022 Texas Instruments Incorporated...
Page 521 If two high priority SOC’s are triggered at the same time, the SOC with the lower number will take precedence. SPRUH18I – JANUARY 2011 – REVISED JUNE 2022 TMS320x2806x Microcontrollers Submit Document Feedback Copyright © 2022 Texas Instruments Incorporated...
Page 522 (value = 7) (value = 7) High Priority High Priority RRPOINTER RRPOINTER (value = 7) (value = 12) Figure 8-6. High Priority Example TMS320x2806x Microcontrollers SPRUH18I – JANUARY 2011 – REVISED JUNE 2022 Submit Document Feedback Copyright © 2022 Texas Instruments Incorporated...
Page 523 SOCx instead, or even both. In the latter case, both SOCx triggers will start a conversion. Therefore, caution is urged as both SOCx's will store their results to the same ADCRESULTx registers, possibly overwriting each other. SPRUH18I – JANUARY 2011 – REVISED JUNE 2022 TMS320x2806x Microcontrollers Submit Document Feedback Copyright © 2022 Texas Instruments Incorporated...
Page 524 Figure 8-7. Interrupt Structure Note Interrupt generation may be disrupted in non-continuous conversion mode when the interrupt overflow bit in ADCINTOVF is set. TMS320x2806x Microcontrollers SPRUH18I – JANUARY 2011 – REVISED JUNE 2022 Submit Document Feedback Copyright © 2022 Texas Instruments Incorporated...
Page 525 For more information on the Device_cal() function refer to the Boot ROM section in this manual. Texas Instruments cannot assure the parameters specified in the data sheet, if a value other than the factory settings contained in the TI reserved OTP memory is written into the ADC trim registers.
Page 526 *All fractional values are truncated **VREFLO must be tied to ground in this mode. This is done internally on some devices. TMS320x2806x Microcontrollers SPRUH18I – JANUARY 2011 – REVISED JUNE 2022 Submit Document Feedback Copyright © 2022 Texas Instruments Incorporated...
Page 527 13 ADC Clocks Minimum Conversion 1 ADCCLKs 7 ADCCLKs 13 ADC Clocks Figure 8-8. Timing Example For Sequential Mode / Late Interrupt Pulse SPRUH18I – JANUARY 2011 – REVISED JUNE 2022 TMS320x2806x Microcontrollers Submit Document Feedback Copyright © 2022 Texas Instruments Incorporated...
Page 528 13 ADC Clocks Minimum Conversion 1 ADCCLKs 7 ADCCLKs 13 ADC Clocks Figure 8-9. Timing Example For Sequential Mode / Early Interrupt Pulse TMS320x2806x Microcontrollers SPRUH18I – JANUARY 2011 – REVISED JUNE 2022 Submit Document Feedback Copyright © 2022 Texas Instruments Incorporated...
Page 529 Minimum Conversion 1 (A) ADCCLKs 7 ADCCLKs 13 ADC Clocks Figure 8-10. Timing Example For Simultaneous Mode / Late Interrupt Pulse SPRUH18I – JANUARY 2011 – REVISED JUNE 2022 TMS320x2806x Microcontrollers Submit Document Feedback Copyright © 2022 Texas Instruments Incorporated...
Page 530 Minimum Conversion 1 (A) ADCCLKs 7 ADCCLKs 13 ADC Clocks Figure 8-11. Timing Example For Simultaneous Mode / Early Interrupt Pulse TMS320x2806x Microcontrollers SPRUH18I – JANUARY 2011 – REVISED JUNE 2022 Submit Document Feedback Copyright © 2022 Texas Instruments Incorporated...
Page 531 Figure 8-12. Timing Example for NONOVERLAP Mode Note The NONOVERLAP bit in the ADCCTL2 register, when enabled, removes the overlap of sampling and conversion stages. SPRUH18I – JANUARY 2011 – REVISED JUNE 2022 TMS320x2806x Microcontrollers Submit Document Feedback Copyright © 2022 Texas Instruments Incorporated...
Page 533 //Slope of temperature sensor (deg. C / ADC code, fixed pt Q15 format) #define getTempSlope() (*(int (*)(void))0x3D7E82)() //ADC code corresponding to temperature sensor output at 0-degreesC #define getTempOffset() (*(int (*)(void))0x3D7E85)() SPRUH18I – JANUARY 2011 – REVISED JUNE 2022 TMS320x2806x Microcontrollers Submit Document Feedback Copyright © 2022 Texas Instruments Incorporated...
Page 534 The base address of the ADCRESULT registers differs from the base address of the other ADC registers. In the header files, the ADCRESULT registers are found in the AdcResult register file, not in the AdcRegs. TMS320x2806x Microcontrollers SPRUH18I – JANUARY 2011 – REVISED JUNE 2022 Submit Document Feedback Copyright © 2022 Texas Instruments Incorporated...
Page 535 Simultaneous Mode: Cleared 14 ADC clocks after negative edge of S+H pulse ADC is available to sample next channel ADC is busy and cannot sample another channel SPRUH18I – JANUARY 2011 – REVISED JUNE 2022 TMS320x2806x Microcontrollers Submit Document Feedback Copyright © 2022 Texas Instruments Incorporated...
Page 536 ADCINB5 is passed to the ADC module as normal, VREFLO connection to ADCINB5 is disabled VREFLO internally connected to the ADC for sampling TMS320x2806x Microcontrollers SPRUH18I – JANUARY 2011 – REVISED JUNE 2022 Submit Document Feedback Copyright © 2022 Texas Instruments Incorporated...
Page 537 This register is EALLOW protected. Table 8-6. CLKDIV2EN and CLKDIV4EN Usage CLKDIV2EN CLKDIV4EN ADCCLK SYSCLK SYSCLK SYSCLK / 2 SYSCLK / 4 SPRUH18I – JANUARY 2011 – REVISED JUNE 2022 TMS320x2806x Microcontrollers Submit Document Feedback Copyright © 2022 Texas Instruments Incorporated...
Page 538 ADCINTFLG flag is set. Both ADCINTFLG and ADCINTOVF flags must be cleared before normal interrupt operation can resume in non-continuous mode. TMS320x2806x Microcontrollers SPRUH18I – JANUARY 2011 – REVISED JUNE 2022 Submit Document Feedback Copyright © 2022 Texas Instruments Incorporated...
Page 539 HW set will be discarded, no signal will propagate to the PIE form the latch Overflow flag or condition will be generated SPRUH18I – JANUARY 2011 – REVISED JUNE 2022 TMS320x2806x Microcontrollers Submit Document Feedback Copyright © 2022 Texas Instruments Incorporated...
Page 540 Both ADCINTFLG and ADCINTOVF flags must be cleared before normal interrupt operation can resume in non-continuous mode. TMS320x2806x Microcontrollers SPRUH18I – JANUARY 2011 – REVISED JUNE 2022 Submit Document Feedback Copyright © 2022 Texas Instruments Incorporated...
Page 541 ADCINTOVF register, then hardware has priority and the ADCINTOVF bit will be set. SPRUH18I – JANUARY 2011 – REVISED JUNE 2022 TMS320x2806x Microcontrollers Submit Document Feedback Copyright © 2022 Texas Instruments Incorporated...
Page 542 R/W-0 Reserved INT5CONT INT5E INT5SEL R/W-0 R/W-0 R/W-0 LEGEND: R/W = Read/Write; R = Read only; -n = value after reset TMS320x2806x Microcontrollers SPRUH18I – JANUARY 2011 – REVISED JUNE 2022 Submit Document Feedback Copyright © 2022 Texas Instruments Incorporated...
Page 543 ADCINTy pulses are generated whenever an EOC pulse is generated irrespective if the flag bit is cleared or not. INTyE ADCINTy Interrupt Enable ADCINTy is disabled. ADCINTy is enabled. SPRUH18I – JANUARY 2011 – REVISED JUNE 2022 TMS320x2806x Microcontrollers Submit Document Feedback Copyright © 2022 Texas Instruments Incorporated...
Page 544 EOC13 is trigger for ADCINTx EOC14 is trigger for ADCINTx EOC15 is trigger for ADCINTx Invalid value. This register is EALLOW protected. TMS320x2806x Microcontrollers SPRUH18I – JANUARY 2011 – REVISED JUNE 2022 Submit Document Feedback Copyright © 2022 Texas Instruments Incorporated...
Page 545 SOCPRICTL register is written. In the latter case, if a conversion is currently in progress, it will complete and then the new priority will take effect. Others Invalid selection. SPRUH18I – JANUARY 2011 – REVISED JUNE 2022 TMS320x2806x Microcontrollers Submit Document Feedback Copyright © 2022 Texas Instruments Incorporated...
Page 546 SOC0-SOC14 are high priority, SOC15 is in round robin mode. All SOCs are in high priority mode, arbitrated by SOC number Others Invalid selection. This register is EALLOW protected. TMS320x2806x Microcontrollers SPRUH18I – JANUARY 2011 – REVISED JUNE 2022 Submit Document Feedback Copyright © 2022 Texas Instruments Incorporated...
Page 547 EOC8 and EOC9 associated with SOC8 and SOC9 pair. SOC8 and SOC9 results will be placed in ADCRESULT8 and ADCRESULT9 registers, respectively. SPRUH18I – JANUARY 2011 – REVISED JUNE 2022 TMS320x2806x Microcontrollers Submit Document Feedback Copyright © 2022 Texas Instruments Incorporated...
Page 548 EOC0 and EOC1 associated with SOC0 and SOC1 pair. SOC0 and SOC1 results will be placed in ADCRESULT0 and ADCRESULT1 registers, respectively. This register is EALLOW protected. TMS320x2806x Microcontrollers SPRUH18I – JANUARY 2011 – REVISED JUNE 2022 Submit Document Feedback Copyright © 2022 Texas Instruments Incorporated...
Page 549 ADCSOCFRC1 register. No ADCINT will trigger SOCx. ADCINT1 will trigger SOCx. ADCINT2 will trigger SOCx. Invalid selection. This register is EALLOW protected. SPRUH18I – JANUARY 2011 – REVISED JUNE 2022 TMS320x2806x Microcontrollers Submit Document Feedback Copyright © 2022 Texas Instruments Incorporated...
Page 550 ADCSOCOVF1 register will not be affected regardless of whether this bit was previously set or not. TMS320x2806x Microcontrollers SPRUH18I – JANUARY 2011 – REVISED JUNE 2022 Submit Document Feedback Copyright © 2022 Texas Instruments Incorporated...
Page 551 ADCSOCOVF1 register will not be affected regardless of whether the ADCSOCFLG1 bit was previously set or not. SPRUH18I – JANUARY 2011 – REVISED JUNE 2022 TMS320x2806x Microcontrollers Submit Document Feedback Copyright © 2022 Texas Instruments Incorporated...
Page 552 If software tries to set this bit on the same clock cycle that hardware tries to set the overflow bit in the ADCSOCOVF1 register, then hardware has priority and the ADCSOCOVF1 bit will be set. TMS320x2806x Microcontrollers SPRUH18I – JANUARY 2011 – REVISED JUNE 2022 Submit Document Feedback Copyright © 2022 Texas Instruments Incorporated...
Page 553 ADCTRIG18 - ePWM7, ADCSOCB ADCTRIG19 - ePWM8, ADCSOCA ADCTRIG20 - ePWM8, ADCSOCB Others Invalid selection. Reserved Reads return a zero; Writes have no effect. SPRUH18I – JANUARY 2011 – REVISED JUNE 2022 TMS320x2806x Microcontrollers Submit Document Feedback Copyright © 2022 Texas Instruments Incorporated...
Page 554 ADCINA5/ADCINB5 pair ADCINA6/ADCINB6 pair ADCINA7/ADCINB7 pair Invalid selection. Invalid selection. Invalid selection. Invalid selection. Invalid selection. Invalid selection. Invalid selection. Invalid selection. TMS320x2806x Microcontrollers SPRUH18I – JANUARY 2011 – REVISED JUNE 2022 Submit Document Feedback Copyright © 2022 Texas Instruments Incorporated...
Page 555 Other invalid selections: 10h, 11h, 12h, 13h, 14h, 1Dh, 1Eh, 1Fh, 20h, 21h, 2Ah, 2Bh, 2Ch, 2Dh, 2Eh, 37h, 38h, 39h, 3Ah, 3Bh This register is EALLOW protected. SPRUH18I – JANUARY 2011 – REVISED JUNE 2022 TMS320x2806x Microcontrollers Submit Document Feedback Copyright © 2022 Texas Instruments Incorporated...
Page 556 Modification of this default setting can be made to correct any board induced offset. This register is EALLOW protected. TMS320x2806x Microcontrollers SPRUH18I – JANUARY 2011 – REVISED JUNE 2022 Submit Document Feedback Copyright © 2022 Texas Instruments Incorporated...
Page 557 Hysteresis disabled Reserved Reserved COMP1_HYST_ Comparator 1 Hysteresis disable DISABLE Hysteresis enabled Hysteresis disabled Reserved Reserved This register is EALLOW protected. SPRUH18I – JANUARY 2011 – REVISED JUNE 2022 TMS320x2806x Microcontrollers Submit Document Feedback Copyright © 2022 Texas Instruments Incorporated...
Page 558 SOC4, the completed results of those conversions will be placed in ADCRESULT4 and ADCRESULT5. See 1.11 for timings of when this register is written. TMS320x2806x Microcontrollers SPRUH18I – JANUARY 2011 – REVISED JUNE 2022 Submit Document Feedback Copyright © 2022 Texas Instruments Incorporated...
Page 559 Introduction................................560 9.2 Comparator Function............................... 9.3 DAC Reference................................. 9.4 Ramp Generator Input..............................562 Initialization................................563 9.6 Digital Domain Manipulation........................... 9.7 Comparator Registers..............................564 SPRUH18I – JANUARY 2011 – REVISED JUNE 2022 TMS320x2806x Microcontrollers Submit Document Feedback Copyright © 2022 Texas Instruments Incorporated...
Page 560 GPIO Mux DACVAL[9:0] Qualification 10-bit RAMPSTS[15:6] COMPCTL[QUALSEL] VSSA COMPCTL[COMPSOURCE] COMPCTL[SYNCSEL] PWMSYNC1 PWMSYNC2 Ramp Generator COMPSTS PWMSYNCn DACCTL[RAMPSOURCE] Figure 9-1. Comparator Block Diagram TMS320x2806x Microcontrollers SPRUH18I – JANUARY 2011 – REVISED JUNE 2022 Submit Document Feedback Copyright © 2022 Texas Instruments Incorporated...
Page 561 Since the DAC is also in the analog domain it does not require a clock to maintain its voltage output. A clock is required, however, to modify the digital inputs that control the DAC. SPRUH18I – JANUARY 2011 – REVISED JUNE 2022 TMS320x2806x Microcontrollers Submit Document Feedback Copyright © 2022 Texas Instruments Incorporated...
Page 562 The PWMSYNC signal width must be greater than SYSCLK to ensure that the ramp generator is able to detect the PWMSYNC signal. The ramp generator behavior is further illustrated in Figure 9-4. TMS320x2806x Microcontrollers SPRUH18I – JANUARY 2011 – REVISED JUNE 2022 Submit Document Feedback Copyright © 2022 Texas Instruments Incorporated...
Page 564 Ramp Generator Decrement Value (Shadow) Section 9.7.8 Reserved 0x0F Reserved RAMPSTS 0x10 Ramp Generator Status Section 9.7.9 Reserved 0x11-0x1F Reserved This register is EALLOW protected. TMS320x2806x Microcontrollers SPRUH18I – JANUARY 2011 – REVISED JUNE 2022 Submit Document Feedback Copyright © 2022 Texas Instruments Incorporated...
Page 565 Inverting input connected to external pin COMPDACEN Comparator/DAC Enable Comparator/DAC logic is powered down. Comparator/DAC logic is powered up. This register is EALLOW protected. SPRUH18I – JANUARY 2011 – REVISED JUNE 2022 TMS320x2806x Microcontrollers Submit Document Feedback Copyright © 2022 Texas Instruments Incorporated...
Page 566 DAC source control. Select DACVAL or ramp generator to control the DAC. DAC controlled by DACVAL DAC controlled by ramp generator This register is EALLOW protected. TMS320x2806x Microcontrollers SPRUH18I – JANUARY 2011 – REVISED JUNE 2022 Submit Document Feedback Copyright © 2022 Texas Instruments Incorporated...
Page 567 Table 9-9. Ramp Generator Maximum Reference Shadow (RAMPMAXREF_SHDW) Register Field Descriptions Field Value Description 15-0 RAMPMAXREFS 0-FFFFh 16-bit maximum reference shadow value for down ramp generator. SPRUH18I – JANUARY 2011 – REVISED JUNE 2022 TMS320x2806x Microcontrollers Submit Document Feedback Copyright © 2022 Texas Instruments Incorporated...
Page 568 Table 9-12. Ramp Generator Status (RAMPSTS) Register Field Descriptions Field Value Description 15-0 RAMPVALUE 0-FFFFh 16-bit value of down ramp generator. TMS320x2806x Microcontrollers SPRUH18I – JANUARY 2011 – REVISED JUNE 2022 Submit Document Feedback Copyright © 2022 Texas Instruments Incorporated...
Page 569 10.2 CLA Interface................................10.3 CLA and CPU Arbitration............................575 10.4 CLA Configuration and Debug..........................10.5 Pipeline..................................582 10.6 Instruction Set.................................588 10.7 CLA Registers.................................709 SPRUH18I – JANUARY 2011 – REVISED JUNE 2022 TMS320x2806x Microcontrollers Submit Document Feedback Copyright © 2022 Texas Instruments Incorporated...
Page 570 Control Law Accelerator Debug in CCS 4 (Video) • Control Law Accelerator Example Framework (Video) • Enhancing the Computational Performance of the C2000 Microcontroller Family Application Report TMS320x2806x Microcontrollers SPRUH18I – JANUARY 2011 – REVISED JUNE 2022 Submit Document Feedback Copyright © 2022 Texas Instruments Incorporated...
Page 571 MR2 (32) Peripherals MEALLOW MR3 (32) MAR0 (16) MAR1 (16) CPU Read Data Bus Figure 10-1. CLA (Type 0) Block Diagram SPRUH18I – JANUARY 2011 – REVISED JUNE 2022 TMS320x2806x Microcontrollers Submit Document Feedback Copyright © 2022 Texas Instruments Incorporated...
Page 572 RAM is both readable and writable by the CPU. The CLA can perform reads but writes by the CLA are ignored. TMS320x2806x Microcontrollers SPRUH18I – JANUARY 2011 – REVISED JUNE 2022 Submit Document Feedback Copyright © 2022 Texas Instruments Incorporated...
Page 573 ADC value. The CLA pipeline activity for this scenario is shown in Section 10.5. SPRUH18I – JANUARY 2011 – REVISED JUNE 2022 TMS320x2806x Microcontrollers Submit Document Feedback Copyright © 2022 Texas Instruments Incorporated...
Page 574 6. The CLA returns to idle. Once a task completes the next highest-priority pending task is automatically serviced and this sequence repeats. TMS320x2806x Microcontrollers SPRUH18I – JANUARY 2011 – REVISED JUNE 2022 Submit Document Feedback Copyright © 2022 Texas Instruments Incorporated...
Page 575 – CPU reads and writes – CLA reads – CPU debug reads and writes The following accesses are ignored: – CLA writes SPRUH18I – JANUARY 2011 – REVISED JUNE 2022 TMS320x2806x Microcontrollers Submit Document Feedback Copyright © 2022 Texas Instruments Incorporated...
Page 576 – CLA writes are ignored. – The memory block behaves as any normal RAM block mapped to the CPU memory space. TMS320x2806x Microcontrollers SPRUH18I – JANUARY 2011 – REVISED JUNE 2022 Submit Document Feedback Copyright © 2022 Texas Instruments Incorporated...
Page 577 CLA write may be lost if the operation occurs in-between the CPU read and write. For this reason, you should not mix CPU and CLA accesses to same location. SPRUH18I – JANUARY 2011 – REVISED JUNE 2022 TMS320x2806x Microcontrollers Submit Document Feedback Copyright © 2022 Texas Instruments Incorporated...
Page 578 CLA will service its interrupts using the CLA assembly code (or tasks). The main CPU can perform other tasks concurrently with CLA program execution. The CLA Type 0 requires Codegen V5.2.0 or later with the compiler switch: --cla_support=cla0. TMS320x2806x Microcontrollers SPRUH18I – JANUARY 2011 – REVISED JUNE 2022 Submit Document Feedback Copyright © 2022 Texas Instruments Incorporated...
Page 579 RAM once the MMEMCFG[PROGE] bit is set. Allow two SYSCLK cycles for MMEMCFG updates to take effect. SPRUH18I – JANUARY 2011 – REVISED JUNE 2022 TMS320x2806x Microcontrollers Submit Document Feedback Copyright © 2022 Texas Instruments Incorporated...
Page 580 At this point, the CLA will halt and the pipeline will be frozen. The MPC register will reflect the address of the MDEBUGSTOP instruction. TMS320x2806x Microcontrollers SPRUH18I – JANUARY 2011 – REVISED JUNE 2022 Submit Document Feedback Copyright © 2022 Texas Instruments Incorporated...
Page 581 Further single-stepping is ignored once execution halts due to an illegal op-code. To exit this situation, issue either a soft or hard reset of the CLA as described in Section 10.4.5. SPRUH18I – JANUARY 2011 – REVISED JUNE 2022 TMS320x2806x Microcontrollers Submit Document Feedback Copyright © 2022 Texas Instruments Incorporated...
Page 582 8. Write (W): Place the write address and write data on the CLA write data bus. If a memory conflict exists, the W stage will be stalled. TMS320x2806x Microcontrollers SPRUH18I – JANUARY 2011 – REVISED JUNE 2022 Submit Document Feedback Copyright © 2022 Texas Instruments Incorporated...
Page 583 I2 MMOV16 MR2, @Reg2 Table 10-2. Write Followed by Read - Write Occurs First Instruction I1 MMOV16 @Reg1, MR3 I5 MMOV16 MR2, @Reg2 SPRUH18I – JANUARY 2011 – REVISED JUNE 2022 TMS320x2806x Microcontrollers Submit Document Feedback Copyright © 2022 Texas Instruments Incorporated...
Page 584 Example 10-1. To single-step through a branch/call or return, insert the MDEBUGSTOP at least four instructions back and step from there. TMS320x2806x Microcontrollers SPRUH18I – JANUARY 2011 – REVISED JUNE 2022 Submit Document Feedback Copyright © 2022 Texas Instruments Incorporated...
Page 585 ; I4 Will use the new value of MAR0 (20) <Instruction 5> ; I5 Will use the new value of MAR0 (20 ..SPRUH18I – JANUARY 2011 – REVISED JUNE 2022 TMS320x2806x Microcontrollers Submit Document Feedback Copyright © 2022 Texas Instruments Incorporated...
Page 586 (Cycle N-5) RESULT Read Conversion Complete (Cycle N-3) (Cycle N-4) RESULT Read RESULT Latched (Cycle N-3) RESULT Read RESULT Available RESULT TMS320x2806x Microcontrollers SPRUH18I – JANUARY 2011 – REVISED JUNE 2022 Submit Document Feedback Copyright © 2022 Texas Instruments Incorporated...
Page 587 ; <-- MMPYF32 and MADDF32 complete here (MR0 and MR1 are valid) MMPYF32 MR1, MR1, MR0 ; Any instruction, can use MR1 and/or MR0 SPRUH18I – JANUARY 2011 – REVISED JUNE 2022 TMS320x2806x Microcontrollers Submit Document Feedback Copyright © 2022 Texas Instruments Incorporated...
Page 588 MR0 to MR3 registers MR0 to MR3 registers MSTF CLA Floating-point Status Register shift Opcode field indicating the number of bits to shift. TMS320x2806x Microcontrollers SPRUH18I – JANUARY 2011 – REVISED JUNE 2022 Submit Document Feedback Copyright © 2022 Texas Instruments Incorporated...
Page 589 The CLA does not use a data page pointer or a stack pointer. The two addressing modes are encoded as shown Table 10-6. SPRUH18I – JANUARY 2011 – REVISED JUNE 2022 TMS320x2806x Microcontrollers Submit Document Feedback Copyright © 2022 Texas Instruments Incorporated...
Page 590 LSW: 0000 ffee ddcc bbaa MSW: 0111 1010 0000 0000 The two-bit field specifies one of four working registers according to Table 10-8. TMS320x2806x Microcontrollers SPRUH18I – JANUARY 2011 – REVISED JUNE 2022 Submit Document Feedback Copyright © 2022 Texas Instruments Incorporated...
Page 591 MDEBUGSTOP Debug Stop Task........................619 MEALLOW Enable CLA Write Access to EALLOW Protected Registers............620 MEDIS Disable CLA Write Access to EALLOW Protected Registers..............621 SPRUH18I – JANUARY 2011 – REVISED JUNE 2022 TMS320x2806x Microcontrollers Submit Document Feedback Copyright © 2022 Texas Instruments Incorporated...
Page 592 MSUBF32 MRa, #16FHi, MRb 32-Bit Floating-Point Subtraction................696 MSUBF32 MRd, MRe, MRf ||MMOV32 MRa, mem32 32-Bit Floating-Point Subtraction with Parallel Move..698 TMS320x2806x Microcontrollers SPRUH18I – JANUARY 2011 – REVISED JUNE 2022 Submit Document Feedback Copyright © 2022 Texas Instruments Incorporated...
Page 593 MUI32TOF32 MRa, mem32 Convert Unsigned 32-Bit Integer to 32-Bit Floating-Point Value......706 MUI32TOF32 MRa, MRb Convert Unsigned 32-Bit Integer to 32-Bit Floating-Point Value......... 707 MXOR32 MRa, MRb, MRc Bitwise Exclusive Or....................708 SPRUH18I – JANUARY 2011 – REVISED JUNE 2022 TMS320x2806x Microcontrollers Submit Document Feedback Copyright © 2022 Texas Instruments Incorporated...
Page 594 ; MR0 = 0.0 MABSF32 MR0, MR0 ; MR0 = 0.0 ZF = 1, NF = 0 See also MNEGF32 MRa, MRb {, CNDF} TMS320x2806x Microcontrollers SPRUH18I – JANUARY 2011 – REVISED JUNE 2022 Submit Document Feedback Copyright © 2022 Texas Instruments Incorporated...
Page 595 MASR32 MRa, #SHIFT MLSL32 MRa, #SHIFT MLSR32 MRa, #SHIFT MOR32 MRa, MRb, MRc MXOR32 MRa, MRb, MRc MSUB32 MRa, MRb, MRc SPRUH18I – JANUARY 2011 – REVISED JUNE 2022 TMS320x2806x Microcontrollers Submit Document Feedback Copyright © 2022 Texas Instruments Incorporated...
Page 596 MADDF32 MRd, MRe, MRf || MMOV32 MRa, mem32 MADDF32 MRd, MRe, MRf || MMOV32 mem32, MRa MMPYF32 MRa, MRb, MRc || MADDF32 MRd, MRe, MRf TMS320x2806x Microcontrollers SPRUH18I – JANUARY 2011 – REVISED JUNE 2022 Submit Document Feedback Copyright © 2022 Texas Instruments Incorporated...
Page 597 LUF = 1 if MADDF32 generates an underflow condition. • LVF = 1 if MADDF32 generates an overflow condition. Pipeline This is a single-cycle instruction. SPRUH18I – JANUARY 2011 – REVISED JUNE 2022 TMS320x2806x Microcontrollers Submit Document Feedback Copyright © 2022 Texas Instruments Incorporated...
Page 598 MADDF32 MRd, MRe, MRf || MMOV32 MRa, mem32 MADDF32 MRd, MRe, MRf || MMOV32 mem32, MRa MMPYF32 MRa, MRb, MRc || MADDF32 MRd, MRe, MRf TMS320x2806x Microcontrollers SPRUH18I – JANUARY 2011 – REVISED JUNE 2022 Submit Document Feedback Copyright © 2022 Texas Instruments Incorporated...
Page 599 MADDF32 MRd, MRe, MRf || MMOV32 MRa, mem32 MADDF32 MRd, MRe, MRf || MMOV32 mem32, MRa MMPYF32 MRa, MRb, MRc || MADDF32 MRd, MRe, MRf SPRUH18I – JANUARY 2011 – REVISED JUNE 2022 TMS320x2806x Microcontrollers Submit Document Feedback Copyright © 2022 Texas Instruments Incorporated...
Page 600 MADDF32 MRa, MRb, MRc MMPYF32 MRa, MRb, MRc || MADDF32 MRd, MRe, MRf MADDF32 MRd, MRe, MRf || MMOV32 MRa, mem32 TMS320x2806x Microcontrollers SPRUH18I – JANUARY 2011 – REVISED JUNE 2022 Submit Document Feedback Copyright © 2022 Texas Instruments Incorporated...
Page 601 == 0) { ZF = 1; NF = 0; }; Pipeline The MADDF32 and the MMOV32 both complete in a single cycle. SPRUH18I – JANUARY 2011 – REVISED JUNE 2022 TMS320x2806x Microcontrollers Submit Document Feedback Copyright © 2022 Texas Instruments Incorporated...
Page 602 MADDF32 MRa, MRb, MRc MADDF32 MRd, MRe, MRf || MMOV32 mem32, MRa MMPYF32 MRa, MRb, MRc || MADDF32 MRd, MRe, MRf TMS320x2806x Microcontrollers SPRUH18I – JANUARY 2011 – REVISED JUNE 2022 Submit Document Feedback Copyright © 2022 Texas Instruments Incorporated...
Page 603 MASR32 MRa, #SHIFT MLSL32 MRa, #SHIFT MLSR32 MRa, #SHIFT MOR32 MRa, MRb, MRc MXOR32 MRa, MRb, MRc MSUB32 MRa, MRb, MRc SPRUH18I – JANUARY 2011 – REVISED JUNE 2022 TMS320x2806x Microcontrollers Submit Document Feedback Copyright © 2022 Texas Instruments Incorporated...
Page 604 MAND32 MRa, MRb, MRc MLSL32 MRa, #SHIFT MLSR32 MRa, #SHIFT MOR32 MRa, MRb, MRc MXOR32 MRa, MRb, MRc MSUB32 MRa, MRb, MRc TMS320x2806x Microcontrollers SPRUH18I – JANUARY 2011 – REVISED JUNE 2022 Submit Document Feedback Copyright © 2022 Texas Instruments Incorporated...
Page 605 MCCNDD or MRCNDD instruction. Refer to the pipeline section for more information. Flags This instruction does not modify flags in the MSTF register. Flag Modified SPRUH18I – JANUARY 2011 – REVISED JUNE 2022 TMS320x2806x Microcontrollers Submit Document Feedback Copyright © 2022 Texas Instruments Incorporated...
Page 606 _Skip: <Destination 1> ; d1 Can be any instruction <Destination 2> ; d2 <Destination 3> ; d3 ..MSTOP ..TMS320x2806x Microcontrollers SPRUH18I – JANUARY 2011 – REVISED JUNE 2022 Submit Document Feedback Copyright © 2022 Texas Instruments Incorporated...
Page 607 Table 10-10. Pipeline Activity For MBCNDD, Branch Not Taken Instruction MBCNDD MBCNDD MBCNDD MBCNDD MBCNDD Table 10-11. Pipeline Activity For MBCNDD, Branch Taken Instruction MBCNDD MBCNDD MBCNDD MBCNDD MBCNDD SPRUH18I – JANUARY 2011 – REVISED JUNE 2022 TMS320x2806x Microcontrollers Submit Document Feedback Copyright © 2022 Texas Instruments Incorporated...
Page 608 ; Executed if (B) branch taken MOR32 MR3, MR2 ; Executed if (B) branch taken MMOV32 @SteadyState, MR3 ; Executed if (B) branch taken MSTOP TMS320x2806x Microcontrollers SPRUH18I – JANUARY 2011 – REVISED JUNE 2022 Submit Document Feedback Copyright © 2022 Texas Instruments Incorporated...
Page 609 ; end of task if (B) branch not taken Skip2: MMOV32 @SteadyState, MR3 ; Executed if (B) branch taken MSTOP See also MCCNDD 16BitDest, CNDF MRCNDD CNDF SPRUH18I – JANUARY 2011 – REVISED JUNE 2022 TMS320x2806x Microcontrollers Submit Document Feedback Copyright © 2022 Texas Instruments Incorporated...
Page 610 MCCNDD, or MRCNDD instruction. Refer to the Pipeline section for more details. Flags This instruction does not modify flags in the MSTF register. Flag Modified TMS320x2806x Microcontrollers SPRUH18I – JANUARY 2011 – REVISED JUNE 2022 Submit Document Feedback Copyright © 2022 Texas Instruments Incorporated...
Page 611 <Destination 8> ; d8 Cannot be stop, branch, call or return <Destination 9> ; d9 Cannot be stop, branch, call or return SPRUH18I – JANUARY 2011 – REVISED JUNE 2022 TMS320x2806x Microcontrollers Submit Document Feedback Copyright © 2022 Texas Instruments Incorporated...
Page 612 The RPC value in the MSTF register will point to the instruction following I7 (instruction I8). See also MBCNDD #16BitDest, CNDF MMOV32 mem32, MSTF MMOV32 MSTF, mem32 TMS320x2806x Microcontrollers SPRUH18I – JANUARY 2011 – REVISED JUNE 2022 Submit Document Feedback Copyright © 2022 Texas Instruments Incorporated...
Page 613 Control Law Accelerator (CLA) MCCNDD 16BitDest {, CNDF} (continued) Call Conditional Delayed MRCNDD CNDF SPRUH18I – JANUARY 2011 – REVISED JUNE 2022 TMS320x2806x Microcontrollers Submit Document Feedback Copyright © 2022 Texas Instruments Incorporated...
Page 614 MCMP32 MR0, MR1 ; NF = 1, ZF = 0 MCMP32 MR1, MR0 ; NF = 0, ZF = 0 See also MADD32 MRa, MRb, MRc TMS320x2806x Microcontrollers SPRUH18I – JANUARY 2011 – REVISED JUNE 2022 Submit Document Feedback Copyright © 2022 Texas Instruments Incorporated...
Page 615 Control Law Accelerator (CLA) MCMP32 MRa, MRb (continued) 32-Bit Integer Compare for Equal, Less Than or Greater Than MSUB32 MRa, MRb, MRc SPRUH18I – JANUARY 2011 – REVISED JUNE 2022 TMS320x2806x Microcontrollers Submit Document Feedback Copyright © 2022 Texas Instruments Incorporated...
Page 616 ; ZF = 1, NF = 0 See also MCMPF32 MRa, #16FHi MMAXF32 MRa, #16FHi MMAXF32 MRa, MRb MMINF32 MRa, #16FHi MMINF32 MRa, MRb TMS320x2806x Microcontrollers SPRUH18I – JANUARY 2011 – REVISED JUNE 2022 Submit Document Feedback Copyright © 2022 Texas Instruments Incorporated...
Page 617 ; ZF = 0, NF = 0 MCMPF32 MR0, #6.5 ; ZF = 0, NF = 1 MCMPF32 MR0, #5.0 ; ZF = 1, NF = 0 SPRUH18I – JANUARY 2011 – REVISED JUNE 2022 TMS320x2806x Microcontrollers Submit Document Feedback Copyright © 2022 Texas Instruments Incorporated...
Page 618 ; End of task See also MCMPF32 MRa, MRb MMAXF32 MRa, #16FHi MMAXF32 MRa, MRb MMINF32 MRa, #16FHi MMINF32 MRa, MRb TMS320x2806x Microcontrollers SPRUH18I – JANUARY 2011 – REVISED JUNE 2022 Submit Document Feedback Copyright © 2022 Texas Instruments Incorporated...
Page 619 This instruction does not modify flags in the MSTF register. Flag Modified Pipeline This is a single-cycle instruction. See also MSTOP SPRUH18I – JANUARY 2011 – REVISED JUNE 2022 TMS320x2806x Microcontrollers Submit Document Feedback Copyright © 2022 Texas Instruments Incorporated...
Page 620 ; Allow CLA write access MMOV16 @_EPwm1Regs.TZSEL.all, MR3 ; Write to TZSEL MEDIS ; Disallow CLA write access MSTOP See also MEDIS TMS320x2806x Microcontrollers SPRUH18I – JANUARY 2011 – REVISED JUNE 2022 Submit Document Feedback Copyright © 2022 Texas Instruments Incorporated...
Page 621 ; Allow CLA write access MMOV16 @_EPwm1Regs.TZSEL.all, MR3 ; Write to TZSEL MEDIS ; Disallow CLA write access MSTOP See also MEALLOW SPRUH18I – JANUARY 2011 – REVISED JUNE 2022 TMS320x2806x Microcontrollers Submit Document Feedback Copyright © 2022 Texas Instruments Incorporated...
Page 622 ; MR0 = Y = Ye*Num MMOV32 @_Dest, MR0 ; Store result MSTOP ; end of task See also MEISQRTF32 MRa, MRb TMS320x2806x Microcontrollers SPRUH18I – JANUARY 2011 – REVISED JUNE 2022 Submit Document Feedback Copyright © 2022 Texas Instruments Incorporated...
Page 623 MMPYF32 MR0, MR1, MR0 ; MR0 = Y = Ye*X MMOV32 @_y, MR0 ; Store Y = sqrt(X) MSTOP ; end of task SPRUH18I – JANUARY 2011 – REVISED JUNE 2022 TMS320x2806x Microcontrollers Submit Document Feedback Copyright © 2022 Texas Instruments Incorporated...
Page 624 Control Law Accelerator (CLA) www.ti.com MEISQRTF32 MRa, MRb (continued) 32-Bit Floating-Point Square-Root Reciprocal Approximation See also MEINVF32 MRa, MRb TMS320x2806x Microcontrollers SPRUH18I – JANUARY 2011 – REVISED JUNE 2022 Submit Document Feedback Copyright © 2022 Texas Instruments Incorporated...
Page 625 MF32TOI16R MRa, MRb MF32TOUI16 MRa, MRb MF32TOUI16R MRa, MRb MI16TOF32 MRa, MRb MI16TOF32 MRa, mem16 MUI16TOF32 MRa, mem16 MUI16TOF32 MRa, MRb SPRUH18I – JANUARY 2011 – REVISED JUNE 2022 TMS320x2806x Microcontrollers Submit Document Feedback Copyright © 2022 Texas Instruments Incorporated...
Page 626 MF32TOI16 MRa, MRb MF32TOUI16 MRa, MRb MF32TOUI16R MRa, MRb MI16TOF32 MRa, MRb MI16TOF32 MRa, mem16 MUI16TOF32 MRa, mem16 MUI16TOF32 MRa, MRb TMS320x2806x Microcontrollers SPRUH18I – JANUARY 2011 – REVISED JUNE 2022 Submit Document Feedback Copyright © 2022 Texas Instruments Incorporated...
Page 627 ; end of task See also MF32TOUI32 MRa, MRb MI32TOF32 MRa, MRb MI32TOF32 MRa, mem32 MUI32TOF32 MRa, MRb MUI32TOF32 MRa, mem32 SPRUH18I – JANUARY 2011 – REVISED JUNE 2022 TMS320x2806x Microcontrollers Submit Document Feedback Copyright © 2022 Texas Instruments Incorporated...
Page 628 MF32TOI16 MRa, MRb MF32TOUI16 MRa, MRb MF32TOUI16R MRa, MRb MI16TOF32 MRa, MRb MI16TOF32 MRa, mem16 MUI16TOF32 MRa, mem16 MUI16TOF32 MRa, MRb TMS320x2806x Microcontrollers SPRUH18I – JANUARY 2011 – REVISED JUNE 2022 Submit Document Feedback Copyright © 2022 Texas Instruments Incorporated...
Page 629 MF32TOI16 MRa, MRb MF32TOI16R MRa, MRb MF32TOUI16 MRa, MRb MI16TOF32 MRa, MRb MI16TOF32 MRa, mem16 MUI16TOF32 MRa, mem16 MUI16TOF32 MRa, MRb SPRUH18I – JANUARY 2011 – REVISED JUNE 2022 TMS320x2806x Microcontrollers Submit Document Feedback Copyright © 2022 Texas Instruments Incorporated...
Page 630 ; MR2 = MF32TOUI32 (MR1) = 0.0 (0x00000000) See also MF32TOI32 MRa, MRb MI32TOF32 MRa, MRb MI32TOF32 MRa, mem32 MUI32TOF32 MRa, MRb MUI32TOF32 MRa, mem32 TMS320x2806x Microcontrollers SPRUH18I – JANUARY 2011 – REVISED JUNE 2022 Submit Document Feedback Copyright © 2022 Texas Instruments Incorporated...
Page 631 This is a single-cycle instruction. Example MMOVIZ MR2, #19.625 ; MR2 = 19.625 (0x419D0000) MFRACF32 MR3, MR2 ; MR3 = MFRACF32(MR2) = 0.625 (0x3F200000)0) SPRUH18I – JANUARY 2011 – REVISED JUNE 2022 TMS320x2806x Microcontrollers Submit Document Feedback Copyright © 2022 Texas Instruments Incorporated...
Page 632 MF32TOI16 MRa, MRb MF32TOI16R MRa, MRb MF32TOUI16 MRa, MRb MF32TOUI16R MRa, MRb MI16TOF32 MRa, mem16 MUI16TOF32 MRa, mem16 MUI16TOF32 MRa, MRb TMS320x2806x Microcontrollers SPRUH18I – JANUARY 2011 – REVISED JUNE 2022 Submit Document Feedback Copyright © 2022 Texas Instruments Incorporated...
Page 633 MF32TOI16 MRa, MRb MF32TOI16R MRa, MRb MF32TOUI16 MRa, MRb MF32TOUI16R MRa, MRb MI16TOF32 MRa, MRb MUI16TOF32 MRa, mem16 MUI16TOF32 MRa, MRb SPRUH18I – JANUARY 2011 – REVISED JUNE 2022 TMS320x2806x Microcontrollers Submit Document Feedback Copyright © 2022 Texas Instruments Incorporated...
Page 634 ; end of task See also MF32TOI32 MRa, MRb MF32TOUI32 MRa, MRb MI32TOF32 MRa, MRb MUI32TOF32 MRa, MRb MUI32TOF32 MRa, mem32 TMS320x2806x Microcontrollers SPRUH18I – JANUARY 2011 – REVISED JUNE 2022 Submit Document Feedback Copyright © 2022 Texas Instruments Incorporated...
Page 635 ; MR3 = MI32TOF32 (MR2) = 286331153.0 (0x4D888888) See also MF32TOI32 MRa, MRb MF32TOUI32 MRa, MRb MI32TOF32 MRa, mem32 MUI32TOF32 MRa, MRb MUI32TOF32 MRa, mem32 SPRUH18I – JANUARY 2011 – REVISED JUNE 2022 TMS320x2806x Microcontrollers Submit Document Feedback Copyright © 2022 Texas Instruments Incorporated...
Page 636 MASR32 MRa, #SHIFT MAND32 MRa, MRb, MRc MLSR32 MRa, #SHIFT MOR32 MRa, MRb, MRc MXOR32 MRa, MRb, MRc MSUB32 MRa, MRb, MRc TMS320x2806x Microcontrollers SPRUH18I – JANUARY 2011 – REVISED JUNE 2022 Submit Document Feedback Copyright © 2022 Texas Instruments Incorporated...
Page 637 MASR32 MRa, #SHIFT MAND32 MRa, MRb, MRc MLSL32 MRa, #SHIFT MOR32 MRa, MRb, MRc MXOR32 MRa, MRb, MRc MSUB32 MRa, MRb, MRc SPRUH18I – JANUARY 2011 – REVISED JUNE 2022 TMS320x2806x Microcontrollers Submit Document Feedback Copyright © 2022 Texas Instruments Incorporated...
Page 638 ZF = 0; if(MRa(30:23) == 0) { ZF = 1; NF = 0; } Pipeline MMACF32 and MMOV32 complete in a single cycle. TMS320x2806x Microcontrollers SPRUH18I – JANUARY 2011 – REVISED JUNE 2022 Submit Document Feedback Copyright © 2022 Texas Instruments Incorporated...
Page 639 || MMPYF32 MR2, MR1, MR0 ; MR2 = Y1*A1 MADDF32 MR3, MR3, MR2 ; MR3 = Y1*A1 + Y2*A2 + X0*B0 + X1*B1 + X2*B2 SPRUH18I – JANUARY 2011 – REVISED JUNE 2022 TMS320x2806x Microcontrollers Submit Document Feedback Copyright © 2022 Texas Instruments Incorporated...
Page 640 MMOV32 @_Y1, MR3 ; Y1 = MR3 MSTOP ; end of task See also MMPYF32 MRa, MRb, MRc || MADDF32 MRd, MRe, MRf TMS320x2806x Microcontrollers SPRUH18I – JANUARY 2011 – REVISED JUNE 2022 Submit Document Feedback Copyright © 2022 Texas Instruments Incorporated...
Page 641 ; MR2 = 5.0, ZF = 0, NF = 1 MAXF32 MR0, MR2 ; MR2 = 5.0, ZF = 1, NF = 0 SPRUH18I – JANUARY 2011 – REVISED JUNE 2022 TMS320x2806x Microcontrollers Submit Document Feedback Copyright © 2022 Texas Instruments Incorporated...
Page 642 ; End of task See also MCMPF32 MRa, MRb MCMPF32 MRa, #16FHi MMAXF32 MRa, #16FHi MMINF32 MRa, MRb MMINF32 MRa, #16FHi TMS320x2806x Microcontrollers SPRUH18I – JANUARY 2011 – REVISED JUNE 2022 Submit Document Feedback Copyright © 2022 Texas Instruments Incorporated...
Page 643 MR2, #-1.0 ; MR2 = -1.5, ZF = 1, NF = 0 See also MMAXF32 MRa, MRb MMINF32 MRa, MRb MMINF32 MRa, #16FHi SPRUH18I – JANUARY 2011 – REVISED JUNE 2022 TMS320x2806x Microcontrollers Submit Document Feedback Copyright © 2022 Texas Instruments Incorporated...
Page 644 ; MR2 = -1.5, ZF = 1, NF = 0 MMINF32 MR1, MR0 ; MR2 = -1.5, ZF = 0, NF = 1 TMS320x2806x Microcontrollers SPRUH18I – JANUARY 2011 – REVISED JUNE 2022 Submit Document Feedback Copyright © 2022 Texas Instruments Incorporated...
Page 645 ; Always executed MNOP ; Always executed MSTOP ; End of task See also MMAXF32 MRa, MRb MMAXF32 MRa, #16FHi MMINF32 MRa, #16FHi SPRUH18I – JANUARY 2011 – REVISED JUNE 2022 TMS320x2806x Microcontrollers Submit Document Feedback Copyright © 2022 Texas Instruments Incorporated...
Page 646 ; MR2 = -1.5, ZF = 1, NF = 0 See also MMAXF32 MRa, #16FHi MMAXF32 MRa, MRb MMINF32 MRa, MRb TMS320x2806x Microcontrollers SPRUH18I – JANUARY 2011 – REVISED JUNE 2022 Submit Document Feedback Copyright © 2022 Texas Instruments Incorporated...
Page 647 ; I3 Cannot use MAR0 <Instruction 4> ; I4 Will use the new value of MAR0 (30) <Instruction 5> ; I5 SPRUH18I – JANUARY 2011 – REVISED JUNE 2022 TMS320x2806x Microcontrollers Submit Document Feedback Copyright © 2022 Texas Instruments Incorporated...
Page 648 MMOV32 MR0,@_TwoPiDivTABLE_SIZE ; I2 MMPYF32 MR1,MR1,MR0 ; I3 MMOV32 MR0,@_Coef3 MMOV32 MR2,*MAR0[#-64]++ ; MR2 = *MAR0, MAR0 += (-64) MSTOP ; end of task TMS320x2806x Microcontrollers SPRUH18I – JANUARY 2011 – REVISED JUNE 2022 Submit Document Feedback Copyright © 2022 Texas Instruments Incorporated...
Page 649 ; end of task ; This task initializes the ConversionCount ; to zero _Cla1Task8: MMOVIZ MR0, #0.0 MMOV16 @_ConversionCount, MR0 MSTOP _ClaT8End: SPRUH18I – JANUARY 2011 – REVISED JUNE 2022 TMS320x2806x Microcontrollers Submit Document Feedback Copyright © 2022 Texas Instruments Incorporated...
Page 650 ; I3 Cannot use MAR0 <Instruction 4> ; I4 Will use the new value of MAR0 (20) <Instruction 5> ; I5 ..TMS320x2806x Microcontrollers SPRUH18I – JANUARY 2011 – REVISED JUNE 2022 Submit Document Feedback Copyright © 2022 Texas Instruments Incorporated...
Page 651 ; If branch taken, restart count MSTOP ; end of task ; This task initializes the ConversionCount ; to zero _Cla1Task8: SPRUH18I – JANUARY 2011 – REVISED JUNE 2022 TMS320x2806x Microcontrollers Submit Document Feedback Copyright © 2022 Texas Instruments Incorporated...
Page 652 Control Law Accelerator (CLA) www.ti.com MMOV16 MARx, mem16 (continued) Load MAR1 with 16-bit Value MMOVIZ MR0, #0.0 MMOV16 @_ConversionCount, MR0 MSTOP _ClaT8End: TMS320x2806x Microcontrollers SPRUH18I – JANUARY 2011 – REVISED JUNE 2022 Submit Document Feedback Copyright © 2022 Texas Instruments Incorporated...
Page 653 Store the contents of MAR0 or MAR1 in the 16-bit memory location pointed to by mem16. [mem16] = MAR0; Flags No flags MSTF flags are affected. Flag Modified Pipeline This is a single-cycle instruction. SPRUH18I – JANUARY 2011 – REVISED JUNE 2022 TMS320x2806x Microcontrollers Submit Document Feedback Copyright © 2022 Texas Instruments Incorporated...
Page 654 MMOV16 *MAR1, MR2 ; Store ADCRESULT1 MBCNDD _RestartCount, GEQ ; If count >= NUM_DATA_POINTS MMOVIZ MR1, #0.0 ; Always executed: MR1=0 TMS320x2806x Microcontrollers SPRUH18I – JANUARY 2011 – REVISED JUNE 2022 Submit Document Feedback Copyright © 2022 Texas Instruments Incorporated...
Page 655 ; This task initializes the ConversionCount ; to zero _Cla1Task8: MMOVIZ MR0, #0.0 MMOV16 @_ConversionCount, MR0 MSTOP _ClaT8End: See also MMOVIZ MRa, #16FHi MMOVXI MRa, #16FLoHex SPRUH18I – JANUARY 2011 – REVISED JUNE 2022 TMS320x2806x Microcontrollers Submit Document Feedback Copyright © 2022 Texas Instruments Incorporated...
Page 656 ; MR3 = (A + B + C + D) + E MMOV32 @_Result, MR3 ; Store the result MSTOP ; end of task See also MMOV32 mem32, MSTF TMS320x2806x Microcontrollers SPRUH18I – JANUARY 2011 – REVISED JUNE 2022 Submit Document Feedback Copyright © 2022 Texas Instruments Incorporated...
Page 657 | RPC updated with MPC+1 MNOP |R1| MNOP |R2| MNOP |E | execution branches to _bar See also MMOV32 mem32, MRa SPRUH18I – JANUARY 2011 – REVISED JUNE 2022 TMS320x2806x Microcontrollers Submit Document Feedback Copyright © 2022 Texas Instruments Incorporated...
Page 658 == 0) { ZF = 1; NF = 0; } else No flags modified; Pipeline This is a single-cycle instruction. TMS320x2806x Microcontrollers SPRUH18I – JANUARY 2011 – REVISED JUNE 2022 Submit Document Feedback Copyright © 2022 Texas Instruments Incorporated...
Page 659 MMOV32 @_Y, MR3 ; Store Y MSTOP ; end of task See also MMOV32 MRa, MRb {, CNDF} MMOVD32 MRa, mem32 SPRUH18I – JANUARY 2011 – REVISED JUNE 2022 TMS320x2806x Microcontrollers Submit Document Feedback Copyright © 2022 Texas Instruments Incorporated...
Page 660 NF = MRa(31); ZF = 0; if(MRa(30:23) == 0) {ZF = 1; NF = 0;} else No flags modified; Pipeline This is a single-cycle instruction. TMS320x2806x Microcontrollers SPRUH18I – JANUARY 2011 – REVISED JUNE 2022 Submit Document Feedback Copyright © 2022 Texas Instruments Incorporated...
Page 661 ; true, MR2 = MR1 = 2.0 MMOV32 MR2, MR0, LT ; false, does not load MR2 MSTOP See also MMOV32 MRa, mem32 {,CNDF} SPRUH18I – JANUARY 2011 – REVISED JUNE 2022 TMS320x2806x Microcontrollers Submit Document Feedback Copyright © 2022 Texas Instruments Incorporated...
Page 662 Loading the status register will overwrite all flags and the RPC field. The MEALLOW field is not affected. Pipeline This is a single-cycle instruction. See also MMOV32 mem32, MSTF TMS320x2806x Microcontrollers SPRUH18I – JANUARY 2011 – REVISED JUNE 2022 Submit Document Feedback Copyright © 2022 Texas Instruments Incorporated...
Page 663 ; MR3 = Y1*A1 + Y2*A2 + X0*B0 + X1*B1 + X2*B2 MMOV32 @_Y1, MR3 ; Y1 = MR3 MSTOP ; end of task SPRUH18I – JANUARY 2011 – REVISED JUNE 2022 TMS320x2806x Microcontrollers Submit Document Feedback Copyright © 2022 Texas Instruments Incorporated...
Page 664 Control Law Accelerator (CLA) www.ti.com MMOVD32 MRa, mem32 (continued) Move 32-Bit Value from Memory with Data Copy See also MMOV32 MRa, mem32 {,CNDF} TMS320x2806x Microcontrollers SPRUH18I – JANUARY 2011 – REVISED JUNE 2022 Submit Document Feedback Copyright © 2022 Texas Instruments Incorporated...
Page 665 ; Assembler converts this instruction as ; MMOVIZ MR3, #0x4144 ; MMOVXI MR3, #0x3D71 See also MMOVIZ MRa, #16FHi MMOVXI MRa, #16FLoHex MMOVI32 MRa, #32FHex SPRUH18I – JANUARY 2011 – REVISED JUNE 2022 TMS320x2806x Microcontrollers Submit Document Feedback Copyright © 2022 Texas Instruments Incorporated...
Page 666 ; I3 Cannot use MAR0 <Instruction 4> ; I4 Will use the new value of MAR0 (20) <Instruction 5> ; I5 ..TMS320x2806x Microcontrollers SPRUH18I – JANUARY 2011 – REVISED JUNE 2022 Submit Document Feedback Copyright © 2022 Texas Instruments Incorporated...
Page 667 Load the Auxiliary Register with the 16-Bit Immediate Value Table 10-16. Pipeline Activity For MMOVI16 MAR0/MAR1, #16I Instruction MMOVI16 MAR0, #_X MMOVI16 MMOVI16 MMOVI16 MMOVI16 MMOVI16 MMOVI16 MMOVI16 SPRUH18I – JANUARY 2011 – REVISED JUNE 2022 TMS320x2806x Microcontrollers Submit Document Feedback Copyright © 2022 Texas Instruments Incorporated...
Page 668 MOVI32 MR0, #0x00004040 ; MR0 = 0x00004040 ; Assembler converts this instruction as ; MMOVIZ MR0, #0x0000 ; MMOVXI MR0, #0x4040 TMS320x2806x Microcontrollers SPRUH18I – JANUARY 2011 – REVISED JUNE 2022 Submit Document Feedback Copyright © 2022 Texas Instruments Incorporated...
Page 669 Load the 32-Bits of a 32-Bit Floating-Point Register with the Immediate See also MMOVIZ MRa, #16FHi MMOVXI MRa, #16FLoHex MMOVF32 MRa, #32F SPRUH18I – JANUARY 2011 – REVISED JUNE 2022 TMS320x2806x Microcontrollers Submit Document Feedback Copyright © 2022 Texas Instruments Incorporated...
Page 670 ; MR2 = 0x40490000 MMOVXI MR2, #0x0FDB ; MR2 = 0x40490FDB See also MMOVF32 MRa, #32F MMOVI32 MRa, #32FHex MMOVXI MRa, #16FLoHex TMS320x2806x Microcontrollers SPRUH18I – JANUARY 2011 – REVISED JUNE 2022 Submit Document Feedback Copyright © 2022 Texas Instruments Incorporated...
Page 671 The MSTF register flags are modified based on the integer results of the operation. NF = 0; if (MRa(31:0)== 0) { ZF = 1; } Pipeline This is a single-cycle instruction. SPRUH18I – JANUARY 2011 – REVISED JUNE 2022 TMS320x2806x Microcontrollers Submit Document Feedback Copyright © 2022 Texas Instruments Incorporated...
Page 672 ; Load MR0 with pi = 3.141593 (0x40490FDB) MMOVIZ MR0,#0x4049 ; MR0 = 0x40490000 MMOVXI MR0,#0x0FDB ; MR0 = 0x40490FDB See also MMOVIZ MRa, #16FHi TMS320x2806x Microcontrollers SPRUH18I – JANUARY 2011 – REVISED JUNE 2022 Submit Document Feedback Copyright © 2022 Texas Instruments Incorporated...
Page 673 MMPYF32 MRd, MRe, MRf || MMOV32 mem32, MRa MMPYF32 MRa, MRb, MRc || MSUBF32 MRd, MRe, MRf MMACF32 MR3, MR2, MRd, MRe, MRf || MMOV32 MRa, mem32 SPRUH18I – JANUARY 2011 – REVISED JUNE 2022 TMS320x2806x Microcontrollers Submit Document Feedback Copyright © 2022 Texas Instruments Incorporated...
Page 674 MR0, #0x4040, MR3 ; MR0 = 0x4040 * MR3 = 6.0 (0x40C00000) MMOV32 @_X, MR0 ; Save the result in variable X TMS320x2806x Microcontrollers SPRUH18I – JANUARY 2011 – REVISED JUNE 2022 Submit Document Feedback Copyright © 2022 Texas Instruments Incorporated...
Page 675 ; end of task See also MMPYF32 MRa, MRb, #16FHi MMPYF32 MRa, MRb, MRc MMPYF32 MRa, MRb, MRc || MADDF32 MRd, MRe, MRf SPRUH18I – JANUARY 2011 – REVISED JUNE 2022 TMS320x2806x Microcontrollers Submit Document Feedback Copyright © 2022 Texas Instruments Incorporated...
Page 676 MR0, MR3, #0x4040 ; MR0 = MR3 * 0x4040 = 6.0 (0x40C00000) MMOV32 @_X, MR0 ; Save the result in variable X TMS320x2806x Microcontrollers SPRUH18I – JANUARY 2011 – REVISED JUNE 2022 Submit Document Feedback Copyright © 2022 Texas Instruments Incorporated...
Page 677 MMOV32 @_Y, MR2 ; store result MSTOP ; end of task See also MMPYF32 MRa, #16FHi, MRb MMPYF32 MRa, MRb, MRc SPRUH18I – JANUARY 2011 – REVISED JUNE 2022 TMS320x2806x Microcontrollers Submit Document Feedback Copyright © 2022 Texas Instruments Incorporated...
Page 678 LVF = 1 if MMPYF32 or MADDF32 generates an overflow condition. Pipeline Both MMPYF32 and MADDF32 complete in a single cycle. TMS320x2806x Microcontrollers SPRUH18I – JANUARY 2011 – REVISED JUNE 2022 Submit Document Feedback Copyright © 2022 Texas Instruments Incorporated...
Page 679 ; Store the result MSTOP ; end of task See also MMACF32 MR3, MR2, MRd, MRe, MRf || MMOV32 MRa, mem32 SPRUH18I – JANUARY 2011 – REVISED JUNE 2022 TMS320x2806x Microcontrollers Submit Document Feedback Copyright © 2022 Texas Instruments Incorporated...
Page 680 ; Add M*X1 to B1 and store in MR1 MMOV32 @Y1, MR1 ; Store the result MSTOP ; end of task TMS320x2806x Microcontrollers SPRUH18I – JANUARY 2011 – REVISED JUNE 2022 Submit Document Feedback Copyright © 2022 Texas Instruments Incorporated...
Page 681 ; end of task See also MMPYF32 MRd, MRe, MRf || MMOV32 mem32, MRa MMACF32 MR3, MR2, MRd, MRe, MRf || MMOV32 MRa, mem32 SPRUH18I – JANUARY 2011 – REVISED JUNE 2022 TMS320x2806x Microcontrollers Submit Document Feedback Copyright © 2022 Texas Instruments Incorporated...
Page 682 ; end of task See also MMPYF32 MRd, MRe, MRf || MMOV32 MRa, mem32 MMACF32 MR3, MR2, MRd, MRe, MRf || MMOV32 MRa, mem32 TMS320x2806x Microcontrollers SPRUH18I – JANUARY 2011 – REVISED JUNE 2022 Submit Document Feedback Copyright © 2022 Texas Instruments Incorporated...
Page 683 See also MSUBF32 MRa, MRb, MRc MSUBF32 MRd, MRe, MRf || MMOV32 MRa, mem32 MSUBF32 MRd, MRe, MRf || MMOV32 mem32, MRa SPRUH18I – JANUARY 2011 – REVISED JUNE 2022 TMS320x2806x Microcontrollers Submit Document Feedback Copyright © 2022 Texas Instruments Incorporated...
Page 684 All other conditions will not modify these flags. Flags This instruction modifies the following flags in the MSTF register: Flag Modified Pipeline This is a single-cycle instruction. TMS320x2806x Microcontrollers SPRUH18I – JANUARY 2011 – REVISED JUNE 2022 Submit Document Feedback Copyright © 2022 Texas Instruments Incorporated...
Page 685 ; MR0 = Y = Ye*Num MMOV32 @_Dest, MR0 ; Store result MSTOP ; end of task See also MABSF32 MRa, MRb SPRUH18I – JANUARY 2011 – REVISED JUNE 2022 TMS320x2806x Microcontrollers Submit Document Feedback Copyright © 2022 Texas Instruments Incorporated...
Page 686 MNOP ; Pad to seperate MBCNDD and MSTOP MNOP ; Pad to seperate MBCNDD and MSTOP MSTOP ; End of task TMS320x2806x Microcontrollers SPRUH18I – JANUARY 2011 – REVISED JUNE 2022 Submit Document Feedback Copyright © 2022 Texas Instruments Incorporated...
Page 687 ; 1010 OR 1100 = 1110 (E) MOR32 MR2, MR1, MR0 ; MR3 = 0x5555FEFE See also MAND32 MRa, MRb, MRc MXOR32 MRa, MRb, MRc SPRUH18I – JANUARY 2011 – REVISED JUNE 2022 TMS320x2806x Microcontrollers Submit Document Feedback Copyright © 2022 Texas Instruments Incorporated...
Page 688 The effective number of cycles for a return can, therefore, range from 1 to 7 cycles. The number of cycles for a return taken may not be the same as for a return not taken. TMS320x2806x Microcontrollers SPRUH18I – JANUARY 2011 – REVISED JUNE 2022 Submit Document Feedback Copyright © 2022 Texas Instruments Incorporated...
Page 689 – These instructions must not be the following: MSTOP, MDEBUGSTOP, MBCNDD, MCCNDD or MRCNDD. SPRUH18I – JANUARY 2011 – REVISED JUNE 2022 TMS320x2806x Microcontrollers Submit Document Feedback Copyright © 2022 Texas Instruments Incorporated...
Page 690 MRCNDD etc......See also MBCNDD #16BitDest, CNDF MCCNDD 16BitDest, CNDF MMOV32 mem32, MSTF MMOV32 MSTF, mem32 TMS320x2806x Microcontrollers SPRUH18I – JANUARY 2011 – REVISED JUNE 2022 Submit Document Feedback Copyright © 2022 Texas Instruments Incorporated...
Page 691 MSTFLG operation as shown below: MSETFLG RNDF32=0, TF=0, NF=1; FLAG = 11000100; VALUE = 00XXX1XX; See also MMOV32 mem32, MSTF MMOV32 MSTF, mem32 SPRUH18I – JANUARY 2011 – REVISED JUNE 2022 TMS320x2806x Microcontrollers Submit Document Feedback Copyright © 2022 Texas Instruments Incorporated...
Page 692 The MSTOP instruction cannot be placed 3 instructions before or after a MBCNDD, MCCNDD, or MRCNDD instruction. Flags This instruction does not modify flags in the MSTF register. Flag Modified TMS320x2806x Microcontrollers SPRUH18I – JANUARY 2011 – REVISED JUNE 2022 Submit Document Feedback Copyright © 2022 Texas Instruments Incorporated...
Page 693 MR3, MR3, MR2 ; A + B + C = 6 (0x0000006) MMOV32 @_y2, MR3 ; Store y2 MSTOP ; End of task See also MDEBUGSTOP SPRUH18I – JANUARY 2011 – REVISED JUNE 2022 TMS320x2806x Microcontrollers Submit Document Feedback Copyright © 2022 Texas Instruments Incorporated...
Page 694 MAND32 MRa, MRb, MRc MASR32 MRa, #SHIFT MLSL32 MRa, #SHIFT MLSR32 MRa, #SHIFT MOR32 MRa, MRb, MRc MXOR32 MRa, MRb, MRc TMS320x2806x Microcontrollers SPRUH18I – JANUARY 2011 – REVISED JUNE 2022 Submit Document Feedback Copyright © 2022 Texas Instruments Incorporated...
Page 695 MSUBF32 MRd, MRe, MRf || MMOV32 MRa, mem32 MSUBF32 MRd, MRe, MRf || MMOV32 mem32, MRa MMPYF32 MRa, MRb, MRc || MSUBF32 MRd, MRe, MRf SPRUH18I – JANUARY 2011 – REVISED JUNE 2022 TMS320x2806x Microcontrollers Submit Document Feedback Copyright © 2022 Texas Instruments Incorporated...
Page 696 MR0, MR1, MR0 ; MR0 = Y = Ye*X MMOV32 @_y, MR0 ; Store Y = sqrt(X) MSTOP ; end of task TMS320x2806x Microcontrollers SPRUH18I – JANUARY 2011 – REVISED JUNE 2022 Submit Document Feedback Copyright © 2022 Texas Instruments Incorporated...
Page 697 MSUBF32 MRd, MRe, MRf || MMOV32 MRa, mem32 MSUBF32 MRd, MRe, MRf || MMOV32 mem32, MRa MMPYF32 MRa, MRb, MRc || MSUBF32 MRd, MRe, MRf SPRUH18I – JANUARY 2011 – REVISED JUNE 2022 TMS320x2806x Microcontrollers Submit Document Feedback Copyright © 2022 Texas Instruments Incorporated...
Page 698 == 0) { ZF = 1; NF = 0; } See also MSUBF32 MRa, MRb, MRc MSUBF32 MRa, #16FHi, MRb MMPYF32 MRa, MRb, MRc || MSUBF32 MRd, MRe, MRf TMS320x2806x Microcontrollers SPRUH18I – JANUARY 2011 – REVISED JUNE 2022 Submit Document Feedback Copyright © 2022 Texas Instruments Incorporated...
Page 699 MSUBF32 MRa, #16FHi, MRb MSUBF32 MRd, MRe, MRf || MMOV32 MRa, mem32 MMPYF32 MRa, MRb, MRc || MSUBF32 MRd, MRe, MRf SPRUH18I – JANUARY 2011 – REVISED JUNE 2022 TMS320x2806x Microcontrollers Submit Document Feedback Copyright © 2022 Texas Instruments Incorporated...
Page 700 This instruction modifies the following flags in the MSTF register: Flag Modified No flags affected Pipeline This is a single-cycle instruction. TMS320x2806x Microcontrollers SPRUH18I – JANUARY 2011 – REVISED JUNE 2022 Submit Document Feedback Copyright © 2022 Texas Instruments Incorporated...
Page 701 ; Branch if not equal to zero MMOV32 @_Result, MR1 ; Always executed MNOP ; Always executed MNOP ; Always executed MSTOP ; End of task SPRUH18I – JANUARY 2011 – REVISED JUNE 2022 TMS320x2806x Microcontrollers Submit Document Feedback Copyright © 2022 Texas Instruments Incorporated...
Page 702 Note: If (CNDF == UNC or UNCF), the TF flag will be set to 1. Pipeline This is a single-cycle instruction. TMS320x2806x Microcontrollers SPRUH18I – JANUARY 2011 – REVISED JUNE 2022 Submit Document Feedback Copyright © 2022 Texas Instruments Incorporated...
Page 703 MSTOP ; end of task if (B) branch not taken _Skip2: MMOV32 @_SteadyState, MR3 ; Executed if (B) branch taken MSTOP SPRUH18I – JANUARY 2011 – REVISED JUNE 2022 TMS320x2806x Microcontrollers Submit Document Feedback Copyright © 2022 Texas Instruments Incorporated...
Page 704 MF32TOI16 MRa, MRb MF32TOI16R MRa, MRb MF32TOUI16 MRa, MRb MF32TOUI16R MRa, MRb MI16TOF32 MRa, MRb MI16TOF32 MRa, mem16 MUI16TOF32 MRa, MRb TMS320x2806x Microcontrollers SPRUH18I – JANUARY 2011 – REVISED JUNE 2022 Submit Document Feedback Copyright © 2022 Texas Instruments Incorporated...
Page 705 MF32TOI16 MRa, MRb MF32TOI16R MRa, MRb MF32TOUI16 MRa, MRb MF32TOUI16R MRa, MRb MI16TOF32 MRa, MRb MI16TOF32 MRa, mem16 MUI16TOF32 MRa, mem16 SPRUH18I – JANUARY 2011 – REVISED JUNE 2022 TMS320x2806x Microcontrollers Submit Document Feedback Copyright © 2022 Texas Instruments Incorporated...
Page 706 ; end of task See also MF32TOI32 MRa, MRb MF32TOUI32 MRa, MRb MI32TOF32 MRa, mem32 MI32TOF32 MRa, MRb MUI32TOF32 MRa, MRb TMS320x2806x Microcontrollers SPRUH18I – JANUARY 2011 – REVISED JUNE 2022 Submit Document Feedback Copyright © 2022 Texas Instruments Incorporated...
Page 707 ; MR3 = MUI32TOF32 (MR3) = 2147488017.0 (0x4F000011) See also MF32TOI32 MRa, MRb MF32TOUI32 MRa, MRb MI32TOF32 MRa, mem32 MI32TOF32 MRa, MRb MUI32TOF32 MRa, mem32 SPRUH18I – JANUARY 2011 – REVISED JUNE 2022 TMS320x2806x Microcontrollers Submit Document Feedback Copyright © 2022 Texas Instruments Incorporated...
Page 708 ; 1010 XOR 1100 = 0110 (6) MXOR32 MR2, MR1, MR0 ; MR3 = 0x01675476 See also MAND32 MRa, MRb, MRc MOR32 MRa, MRb, MRc TMS320x2806x Microcontrollers SPRUH18I – JANUARY 2011 – REVISED JUNE 2022 Submit Document Feedback Copyright © 2022 Texas Instruments Incorporated...
Page 709 The main C28x CPU only has read access to the CLA execution registers for debug purposes. The main CPU cannot perform CPU or debugger writes to these registers. SPRUH18I – JANUARY 2011 – REVISED JUNE 2022 TMS320x2806x Microcontrollers Submit Document Feedback Copyright © 2022 Texas Instruments Incorporated...
Page 710 There is one MVECT register per task. Interrupt 1 uses MVECT1, interrupt 2 uses MVECT2 and so forth. These registers are protected by EALLOW and the dual code security module. TMS320x2806x Microcontrollers SPRUH18I – JANUARY 2011 – REVISED JUNE 2022 Submit Document Feedback Copyright © 2022 Texas Instruments Incorporated...
Page 711 Writing a 1 will cause a hard reset of the CLA. This will set all CLA registers to their default state. This register is protected by EALLOW and the dual code security module. SPRUH18I – JANUARY 2011 – REVISED JUNE 2022 TMS320x2806x Microcontrollers Submit Document Feedback Copyright © 2022 Texas Instruments Incorporated...
Page 712 CLA data SARAM block 2 is mapped to the CLA space. The RAM2CPUE bit determines the CPU access to this memory TMS320x2806x Microcontrollers SPRUH18I – JANUARY 2011 – REVISED JUNE 2022 Submit Document Feedback Copyright © 2022 Texas Instruments Incorporated...
Page 713 CPU debug reads (ignore writes) when the CLA is running. When the CLA is halted or idle then normal CPU debug read and write access can be performed SPRUH18I – JANUARY 2011 – REVISED JUNE 2022 TMS320x2806x Microcontrollers Submit Document Feedback Copyright © 2022 Texas Instruments Incorporated...
Page 714 No interrupt source for task 6. 1000 eCAP1 is the input for interrupt task 6. (ECAP1_INT) Other No interrupt source for task 6. TMS320x2806x Microcontrollers SPRUH18I – JANUARY 2011 – REVISED JUNE 2022 Submit Document Feedback Copyright © 2022 Texas Instruments Incorporated...
Page 715 MIER register and no other higher priority task is pending. The bits can also be cleared manually by writing to the MICLR register. Writes to the MIFR register are ignored. SPRUH18I – JANUARY 2011 – REVISED JUNE 2022 TMS320x2806x Microcontrollers Submit Document Feedback Copyright © 2022 Texas Instruments Incorporated...
Page 716 A task 1 interrupt has been received and is pending execution. This register is protected by the dual code security module. TMS320x2806x Microcontrollers SPRUH18I – JANUARY 2011 – REVISED JUNE 2022 Submit Document Feedback Copyright © 2022 Texas Instruments Incorporated...
Page 717 A task 1 interrupt overflow has not occurred. (default) A task 1 interrupt overflow has occurred. This register is protected by the dual code security module. SPRUH18I – JANUARY 2011 – REVISED JUNE 2022 TMS320x2806x Microcontrollers Submit Document Feedback Copyright © 2022 Texas Instruments Incorporated...
Page 718 Write a 1 to force the task 1 interrupt. This register is protected by EALLOW and the dual code security module. TMS320x2806x Microcontrollers SPRUH18I – JANUARY 2011 – REVISED JUNE 2022 Submit Document Feedback Copyright © 2022 Texas Instruments Incorporated...
Page 719 Write a 1 to clear the task 1 interrupt flag. This register is protected by EALLOW and the dual code security module. SPRUH18I – JANUARY 2011 – REVISED JUNE 2022 TMS320x2806x Microcontrollers Submit Document Feedback Copyright © 2022 Texas Instruments Incorporated...
Page 720 Write a 1 to clear the task 1 interrupt overflow flag. This register is protected by EALLOW and the dual code security module. TMS320x2806x Microcontrollers SPRUH18I – JANUARY 2011 – REVISED JUNE 2022 Submit Document Feedback Copyright © 2022 Texas Instruments Incorporated...
Page 721 Task 3 interrupt is enabled. INT2 Task 2 Interrupt Enable Task 2 interrupt is disabled. (default) Task 2 interrupt is enabled. SPRUH18I – JANUARY 2011 – REVISED JUNE 2022 TMS320x2806x Microcontrollers Submit Document Feedback Copyright © 2022 Texas Instruments Incorporated...
Page 722 Task 1 interrupt is disabled. (default) Task 1 interrupt is enabled. This register is protected by EALLOW and the dual code security module. TMS320x2806x Microcontrollers SPRUH18I – JANUARY 2011 – REVISED JUNE 2022 Submit Document Feedback Copyright © 2022 Texas Instruments Incorporated...
Page 723 Task 1 Run Status Task 1 is not executing. (default) Task 1 is executing. This register is protected by the dual code security module. SPRUH18I – JANUARY 2011 – REVISED JUNE 2022 TMS320x2806x Microcontrollers Submit Document Feedback Copyright © 2022 Texas Instruments Incorporated...
Page 724 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 LEGEND: R/W = Read/Write; R = Read only; -n = value after reset TMS320x2806x Microcontrollers SPRUH18I – JANUARY 2011 – REVISED JUNE 2022 Submit Document Feedback Copyright © 2022 Texas Instruments Incorporated...
Page 725 The MSETFLG and MMOV32 MSTF, mem32 instructions can also be used to modify this flag. The value is not negative. The value is negative. SPRUH18I – JANUARY 2011 – REVISED JUNE 2022 TMS320x2806x Microcontrollers Submit Document Feedback Copyright © 2022 Texas Instruments Incorporated...
Page 726 A negative zero floating-point value is treated as a positive zero value when configuring the ZF and NF flags. A DeNorm floating-point value is treated as a positive zero value when configuring the ZF and NF flags. TMS320x2806x Microcontrollers SPRUH18I – JANUARY 2011 – REVISED JUNE 2022 Submit Document Feedback Copyright © 2022 Texas Instruments Incorporated...
Page 727 11.4 Pipeline Timing and Throughput...........................732 11.5 CPU Arbitration...............................733 11.6 Channel Priority..............................11.7 Address Pointer and Transfer Control........................735 11.8 Overrun Detection Feature............................ 11.9 DMA Registers................................ SPRUH18I – JANUARY 2011 – REVISED JUNE 2022 TMS320x2806x Microcontrollers Submit Document Feedback Copyright © 2022 Texas Instruments Incorporated...
Page 728 (ePWM2-ePWM7) can trigger DMA using PERINTSEL. • Word Size: 16-bit or 32-bit (McBSP limited to 16-bit) • Throughput: 4 cycles/word (5 cycles/word for McBSP reads) TMS320x2806x Microcontrollers SPRUH18I – JANUARY 2011 – REVISED JUNE 2022 Submit Document Feedback Copyright © 2022 Texas Instruments Incorporated...
Page 729 (8Kx16) 6-ch ePWM/ PF3 I/F HRPWM registers SARAM (8Kx16) PF3 I/F SARAM (8Kx16) DMA bus Figure 11-1. DMA Block Diagram SPRUH18I – JANUARY 2011 – REVISED JUNE 2022 TMS320x2806x Microcontrollers Submit Document Feedback Copyright © 2022 Texas Instruments Incorporated...
Page 730 Figure 11-2. Peripheral Interrupt Trigger Input Diagram Table 11-1 shows the interrupt trigger source options that are available for each channel. TMS320x2806x Microcontrollers SPRUH18I – JANUARY 2011 – REVISED JUNE 2022 Submit Document Feedback Copyright © 2022 Texas Instruments Incorporated...
Page 731 • McBSP Data Receive Registers (DRR2/DRR1) and Data Transmit Registers (DXR2/DXR1) • ePWM1-8/HRPWM1-8 Registers • USB Transmit and Receive Endpoints 1-3 SPRUH18I – JANUARY 2011 – REVISED JUNE 2022 TMS320x2806x Microcontrollers Submit Document Feedback Copyright © 2022 Texas Instruments Incorporated...
Page 732 32 bits) the transfer would take: 8 bursts * [(4 cycles/word * 8 words/burst) + 1] = 264 cycles TMS320x2806x Microcontrollers SPRUH18I – JANUARY 2011 – REVISED JUNE 2022 Submit Document Feedback Copyright © 2022 Texas Instruments Incorporated...
Page 733 When CH4 completes its burst, CH5 will be serviced next. Only after CH5 completes will CH1 be serviced. Upon completion of CH1, if there are no more channels pending, the round-robin state machine will enter an idle state. SPRUH18I – JANUARY 2011 – REVISED JUNE 2022 TMS320x2806x Microcontrollers Submit Document Feedback Copyright © 2022 Texas Instruments Incorporated...
Page 734 High-priority mode and ONESHOT mode may not be used at the same time on channel 1. Other channels may use ONESHOT mode when channel 1 is in high-priority mode. TMS320x2806x Microcontrollers SPRUH18I – JANUARY 2011 – REVISED JUNE 2022 Submit Document Feedback Copyright © 2022 Texas Instruments Incorporated...
Page 735 At the beginning of a transfer the shadow register is copied into the active register. The active register performs as the current address pointer. Source/Destination Begin This is the wrap pointer. Address Pointers (SRC/ DST_BEG_ADDR) SPRUH18I – JANUARY 2011 – REVISED JUNE 2022 TMS320x2806x Microcontrollers Submit Document Feedback Copyright © 2022 Texas Instruments Incorporated...
Page 736 This value is a signed 2's compliment number so that the address pointer can be incremented or decremented as required. If no increment is desired, such as TMS320x2806x Microcontrollers SPRUH18I – JANUARY 2011 – REVISED JUNE 2022 Submit Document Feedback Copyright © 2022 Texas Instruments Incorporated...
Page 737 All of the above features and modes are shown in Figure 11-5. SPRUH18I – JANUARY 2011 – REVISED JUNE 2022 TMS320x2806x Microcontrollers Submit Document Feedback Copyright © 2022 Texas Instruments Incorporated...
Page 738 Generate DMACHx interrupt CHINTMODE CONTINUOUS to CPU at end of == 1 == 1 transfer (if enabled) Figure 11-5. DMA State Diagram TMS320x2806x Microcontrollers SPRUH18I – JANUARY 2011 – REVISED JUNE 2022 Submit Document Feedback Copyright © 2022 Texas Instruments Incorporated...
Page 739 CONTROL.CHx CONTROL.CHx [PERINTFLG] MODE.CHx [OVRFLG] [CHINTE] PERx_INT Latch CONTROL.CHx MODE.CHx [ERRCLR] [OVERNITE] Figure 11-6. Overrun Detection Logic SPRUH18I – JANUARY 2011 – REVISED JUNE 2022 TMS320x2806x Microcontrollers Submit Document Feedback Copyright © 2022 Texas Instruments Incorporated...
Page 740 Active Source Begin and Current Address Pointer Registers Section 11.9.20 0x1036 SRC_ADDR Section 11.9.20 0x1038 DST_BEG_ADDR_SHADOW Shadow Destination Begin and Current Address Pointer Registers Section 11.9.21 TMS320x2806x Microcontrollers SPRUH18I – JANUARY 2011 – REVISED JUNE 2022 Submit Document Feedback Copyright © 2022 Texas Instruments Incorporated...
Page 741 LEGEND: R0/S = Read 0/Set; R = Read only; -n = value after reset Table 11-3. DMA Control Register (DMACTRL) Field Descriptions Field Value Description 15-2 Reserved Reserved SPRUH18I – JANUARY 2011 – REVISED JUNE 2022 TMS320x2806x Microcontrollers Submit Document Feedback Copyright © 2022 Texas Instruments Incorporated...
Page 742 (i.e., a NOP instruction) after writing to this bit should be introduced before attempting an access to any other DMA register. TMS320x2806x Microcontrollers SPRUH18I – JANUARY 2011 – REVISED JUNE 2022 Submit Document Feedback Copyright © 2022 Texas Instruments Incorporated...
Page 743 DMA Silicon Revision Bits: These bits specify the DMA revision and are changed if any bug fixes are performed. 0x0000 First release SPRUH18I – JANUARY 2011 – REVISED JUNE 2022 TMS320x2806x Microcontrollers Submit Document Feedback Copyright © 2022 Texas Instruments Incorporated...
Page 744 Channel priority can only be changed when all channels are disabled. A priority reset should be performed before restarting channels after changing priority. TMS320x2806x Microcontrollers SPRUH18I – JANUARY 2011 – REVISED JUNE 2022 Submit Document Feedback Copyright © 2022 Texas Instruments Incorporated...
Page 745 0,0,1 CH 1 0,1,0 CH 2 0,1,1 CH 3 1,0,0 CH 4 1,0,1 CH 5 1,1,0 CH 6 SPRUH18I – JANUARY 2011 – REVISED JUNE 2022 TMS320x2806x Microcontrollers Submit Document Feedback Copyright © 2022 Texas Instruments Incorporated...
Page 746 DMA. Interrupt trigger disabled. Neither the selected peripheral nor software can start a DMA burst. Interrupt trigger enabled. TMS320x2806x Microcontrollers SPRUH18I – JANUARY 2011 – REVISED JUNE 2022 Submit Document Feedback Copyright © 2022 Texas Instruments Incorporated...
Page 747 The overflow interrupt is ORed together with the DMACH interrupt as shown in Figure 11-6. The ADCSYNC only works when the sequencer override bit is set in the ADC sequencer control registers. SPRUH18I – JANUARY 2011 – REVISED JUNE 2022 TMS320x2806x Microcontrollers Submit Document Feedback Copyright © 2022 Texas Instruments Incorporated...
Page 748 The PERINTFRC bit can be used to set the state of this bit to 1 and force a software DMA event. The PERINTCLR bit can be used to clear the state of this bit to 0. TMS320x2806x Microcontrollers SPRUH18I – JANUARY 2011 – REVISED JUNE 2022 Submit Document Feedback Copyright © 2022 Texas Instruments Incorporated...
Page 749 DMA channel out of a HALT condition See Figure 11-5 for the various positions the state machine can be at when HALTED. SPRUH18I – JANUARY 2011 – REVISED JUNE 2022 TMS320x2806x Microcontrollers Submit Document Feedback Copyright © 2022 Texas Instruments Incorporated...
Page 750 2 words left in a burst 31 words left in a burst The above values represent the state of the counter at the HALT conditions. TMS320x2806x Microcontrollers SPRUH18I – JANUARY 2011 – REVISED JUNE 2022 Submit Document Feedback Copyright © 2022 Texas Instruments Incorporated...
Page 751 Sub 1 from address 0xFFFE Sub 2 from address 0xF000 Sub 4096 from address Only values from -4096 to 4095 are valid. SPRUH18I – JANUARY 2011 – REVISED JUNE 2022 TMS320x2806x Microcontrollers Submit Document Feedback Copyright © 2022 Texas Instruments Incorporated...
Page 752 These bits specify the number of bursts to transfer: 0x0000 Transfer 1 burst 0x0001 Transfer 2 bursts 0x0002 Transfer 3 bursts 0xFFFF Transfer 65536 bursts TMS320x2806x Microcontrollers SPRUH18I – JANUARY 2011 – REVISED JUNE 2022 Submit Document Feedback Copyright © 2022 Texas Instruments Incorporated...
Page 753 Sub 1 from address 0xFFFE Sub 2 from address 0xF000 Sub 4096 from address Only values from -4096 to 4095 are valid. SPRUH18I – JANUARY 2011 – REVISED JUNE 2022 TMS320x2806x Microcontrollers Submit Document Feedback Copyright © 2022 Texas Instruments Incorporated...
Page 754 Sub 1 from address 0xFFFE Sub 2 from address 0xF000 Sub 4096 from address Only values from -4096 to 4095 are valid. TMS320x2806x Microcontrollers SPRUH18I – JANUARY 2011 – REVISED JUNE 2022 Submit Document Feedback Copyright © 2022 Texas Instruments Incorporated...
Page 755 0x0002 2 burst left 0xFFFF 65535 burst left The above values represent the state of the counter at the HALT conditions. SPRUH18I – JANUARY 2011 – REVISED JUNE 2022 TMS320x2806x Microcontrollers Submit Document Feedback Copyright © 2022 Texas Instruments Incorporated...
Page 756 Sub 1 from address 0xFFFE Sub 2 from address 0xF000 Sub 4096 from address Only values from -4096 to 4095 are valid. TMS320x2806x Microcontrollers SPRUH18I – JANUARY 2011 – REVISED JUNE 2022 Submit Document Feedback Copyright © 2022 Texas Instruments Incorporated...
Page 757 Table 11-22. Active Source Begin and Current Address Pointer Registers (SRC_BEG_ADDR/ DST_BEG_ADDR) Field Descriptions Field Value Description 31-22 Reserved Reserved 21-0 BEGADDR 22-bit address value SPRUH18I – JANUARY 2011 – REVISED JUNE 2022 TMS320x2806x Microcontrollers Submit Document Feedback Copyright © 2022 Texas Instruments Incorporated...
Page 758 Table 11-24. Active Destination Begin and Current Address Pointer Registers (SRC_ADDR/DST_ADDR) Field Descriptions Field Value Description 31-22 Reserved Reserved 21-0 ADDR 22-bit address value TMS320x2806x Microcontrollers SPRUH18I – JANUARY 2011 – REVISED JUNE 2022 Submit Document Feedback Copyright © 2022 Texas Instruments Incorporated...
Page 759 4-level, receive and transmit FIFO for reducing CPU servicing overhead. 12.1 Introduction................................760 12.2 System-Level Integration............................762 12.3 SPI Operation................................766 12.4 Programming Procedure............................12.5 SPI Registers................................SPRUH18I – JANUARY 2011 – REVISED JUNE 2022 TMS320x2806x Microcontrollers Submit Document Feedback Copyright © 2022 Texas Instruments Incorporated...
Page 760 Delayed transmit control • 3-wire SPI mode • SPISTE inversion for digital audio interface receive mode on devices with two SPI modules TMS320x2806x Microcontrollers SPRUH18I – JANUARY 2011 – REVISED JUNE 2022 Submit Document Feedback Copyright © 2022 Texas Instruments Incorporated...
Page 761 Low speed control prescaler block SPIAENCLK LSPCLK SYSRS SPISIMO SPISOMI GPIO SPICLK SPISTE SPIINT/RXINT TXINT block Figure 12-1. SPI CPU Interface SPRUH18I – JANUARY 2011 – REVISED JUNE 2022 TMS320x2806x Microcontrollers Submit Document Feedback Copyright © 2022 Texas Instruments Incorporated...
Page 762 11b. The internal pullups can be configured in the GPyPUD register. See the GPIO chapter for more details on GPIO mux and settings. TMS320x2806x Microcontrollers SPRUH18I – JANUARY 2011 – REVISED JUNE 2022 Submit Document Feedback Copyright © 2022 Texas Instruments Incorporated...
Page 763 PIE block if TXFFINT is set and the transmit FIFO interrupt is enabled in the SPI module (TXFFIENA = 1). Figure 12-2 Table 12-2 show how these control bits influence the SPI interrupt generation. SPRUH18I – JANUARY 2011 – REVISED JUNE 2022 TMS320x2806x Microcontrollers Submit Document Feedback Copyright © 2022 Texas Instruments Incorporated...
Page 764 For more information on configuring the SPI for DMA transfers, refer to . Figure 12-3 is a block diagram showing the DMA trigger generation from the SPI module. TMS320x2806x Microcontrollers SPRUH18I – JANUARY 2011 – REVISED JUNE 2022 Submit Document Feedback Copyright © 2022 Texas Instruments Incorporated...
Page 765 SPIRXBUF SPISOMI SPIDAT SPISIMO SPITXBUF TX FIFO_0 TX FIFO_1 TXFFST <? SPITXDMA TX FIFO_15 TXFFIL Figure 12-3. SPI DMA Trigger Diagram SPRUH18I – JANUARY 2011 – REVISED JUNE 2022 TMS320x2806x Microcontrollers Submit Document Feedback Copyright © 2022 Texas Instruments Incorporated...
Page 766 Figure 12-5 is a block diagram of the SPI module showing all of the basic control blocks available on the SPI module. TMS320x2806x Microcontrollers SPRUH18I – JANUARY 2011 – REVISED JUNE 2022 Submit Document Feedback Copyright © 2022 Texas Instruments Incorporated...
Page 767 Serial Peripheral Interface (SPI) Figure 12-5. Serial Peripheral Interface Block Diagram SPRUH18I – JANUARY 2011 – REVISED JUNE 2022 TMS320x2806x Microcontrollers Submit Document Feedback Copyright © 2022 Texas Instruments Incorporated...
Page 768 This allows many slave devices to be tied together on the network, although only one slave device is selected at a time. TMS320x2806x Microcontrollers SPRUH18I – JANUARY 2011 – REVISED JUNE 2022 Submit Document Feedback Copyright © 2022 Texas Instruments Incorporated...
Page 769 SPIRXBUF (after transmission) x = 1, if SPISOMI data is high; x = 0, if SPISOMI data is low; master mode is assumed. SPRUH18I – JANUARY 2011 – REVISED JUNE 2022 TMS320x2806x Microcontrollers Submit Document Feedback Copyright © 2022 Texas Instruments Incorporated...
Page 770 Example 12-3 shows how to calculate the baud rate of the SPI module . Example 12-3. Baud Rate Calculation TMS320x2806x Microcontrollers SPRUH18I – JANUARY 2011 – REVISED JUNE 2022 Submit Document Feedback Copyright © 2022 Texas Instruments Incorporated...
Page 771 SPISIMO/ See note SPISOMI SPISTE (Into slave) Receive latch points Note: Previous data bit Figure 12-6. SPICLK Signal Options SPRUH18I – JANUARY 2011 – REVISED JUNE 2022 TMS320x2806x Microcontrollers Submit Document Feedback Copyright © 2022 Texas Instruments Incorporated...
Page 772 RXFFIL. This provides a programmable interrupt trigger for transmit and receive sections of the SPI. The default value for these trigger level bits will be 0x11111 for receive FIFO and 0x00000 for transmit FIFO, respectively. TMS320x2806x Microcontrollers SPRUH18I – JANUARY 2011 – REVISED JUNE 2022 Submit Document Feedback Copyright © 2022 Texas Instruments Incorporated...
Page 773 3-wire master and slave mode. GPIO MUX SPI Module Data RX SPIDAT Free pin Data TX SPIMOMIx Talk SPICTL.1 Figure 12-8. SPI 3-wire Master Mode SPRUH18I – JANUARY 2011 – REVISED JUNE 2022 TMS320x2806x Microcontrollers Submit Document Feedback Copyright © 2022 Texas Instruments Incorporated...
Page 774 SPICTL[TALK] SPISIMO SPISOMI Master Mode 4-wire 3-pin mode Disconnect from SPI TX/RX Slave Mode 4-wire 3-pin mode Disconnect from SPI TX/RX TMS320x2806x Microcontrollers SPRUH18I – JANUARY 2011 – REVISED JUNE 2022 Submit Document Feedback Copyright © 2022 Texas Instruments Incorporated...
Page 775 4. Set SPISWRESET to 1 to release the SPI from the reset state. Note Do not change the SPI configuration when communication is in progress. SPRUH18I – JANUARY 2011 – REVISED JUNE 2022 TMS320x2806x Microcontrollers Submit Document Feedback Copyright © 2022 Texas Instruments Incorporated...
Page 776 09h and the slave receives 0Dh. Master clears the slave SPISTE signal high (inactive). Figure 12-10. Five Bits per Character TMS320x2806x Microcontrollers SPRUH18I – JANUARY 2011 – REVISED JUNE 2022 Submit Document Feedback Copyright © 2022 Texas Instruments Incorporated...
Page 777 // Slave transmits data while(SpiaRegs.SPISTS.bit.INT_FLAG !=1) {} // Wait until data rx’d dummy = SpiaRegs.SPIRXBUF; // Clears junk data from itself SPRUH18I – JANUARY 2011 – REVISED JUNE 2022 TMS320x2806x Microcontrollers Submit Document Feedback Copyright © 2022 Texas Instruments Incorporated...
Page 778 CLK_PHASE bit is 1 (data latched on rising edge of clock), standard right-justified digital audio interface data format is supported as shown in Figure 12-12. TMS320x2806x Microcontrollers SPRUH18I – JANUARY 2011 – REVISED JUNE 2022 Submit Document Feedback Copyright © 2022 Texas Instruments Incorporated...
Page 779 SPIFFRX SPI FIFO Receive Register Section 12.5.2.10 SPIFFCT SPI FIFO Control Register Section 12.5.2.11 SPIPRI SPI Priority Control Register Section 12.5.2.12 SPRUH18I – JANUARY 2011 – REVISED JUNE 2022 TMS320x2806x Microcontrollers Submit Document Feedback Copyright © 2022 Texas Instruments Incorporated...
Page 780 When this variable is used in a register name, an offset, or an address it refers to the value of a register array. TMS320x2806x Microcontrollers SPRUH18I – JANUARY 2011 – REVISED JUNE 2022 Submit Document Feedback Copyright © 2022 Texas Instruments Incorporated...
Page 781 SPICLK will be returned to its inactive state one SPICLK cycle after this bit is set. SPRUH18I – JANUARY 2011 – REVISED JUNE 2022 TMS320x2806x Microcontrollers Submit Document Feedback Copyright © 2022 Texas Instruments Incorporated...
Page 782 0h (R/W) = SPI loopback mode disabled. This is the default value after reset. 1h (R/W) = SPI loopback mode enabled, SIMO/SOMI lines are connected internally. Used for module self-tests. TMS320x2806x Microcontrollers SPRUH18I – JANUARY 2011 – REVISED JUNE 2022 Submit Document Feedback Copyright © 2022 Texas Instruments Incorporated...
Page 783 Bh (R/W) = 12-bit word Ch (R/W) = 13-bit word Dh (R/W) = 14-bit word Eh (R/W) = 15-bit word Fh (R/W) = 16-bit word SPRUH18I – JANUARY 2011 – REVISED JUNE 2022 TMS320x2806x Microcontrollers Submit Document Feedback Copyright © 2022 Texas Instruments Incorporated...
Page 784 Reset type: SYSRSn 0h (R/W) = SPI is configured as a slave. 1h (R/W) = SPI is configured as a master. TMS320x2806x Microcontrollers SPRUH18I – JANUARY 2011 – REVISED JUNE 2022 Submit Document Feedback Copyright © 2022 Texas Instruments Incorporated...
Page 785 The SPI INT FLAG bit (SPISTS.6) is unaffected by this bit. Reset type: SYSRSn 0h (R/W) = Disables the interrupt. 1h (R/W) = Enables the interrupt. SPRUH18I – JANUARY 2011 – REVISED JUNE 2022 TMS320x2806x Microcontrollers Submit Document Feedback Copyright © 2022 Texas Instruments Incorporated...
Page 786 This will alleviate any possible doubt as to the source of the interrupt when the next byte is received. TMS320x2806x Microcontrollers SPRUH18I – JANUARY 2011 – REVISED JUNE 2022 Submit Document Feedback Copyright © 2022 Texas Instruments Incorporated...
Page 787 Reset type: SYSRSn 0h (R/W) = Transmit buffer is not full. 1h (R/W) = Transmit buffer is full. RESERVED Reserved SPRUH18I – JANUARY 2011 – REVISED JUNE 2022 TMS320x2806x Microcontrollers Submit Document Feedback Copyright © 2022 Texas Instruments Incorporated...
Page 788 4h (R/W) = SPI Baud Rate = LSPCLK/5 7Eh (R/W) = SPI Baud Rate = LSPCLK/127 7Fh (R/W) = SPI Baud Rate = LSPCLK/128 TMS320x2806x Microcontrollers SPRUH18I – JANUARY 2011 – REVISED JUNE 2022 Submit Document Feedback Copyright © 2022 Texas Instruments Incorporated...
Page 789 SPI more accurately. It is recommended that you view SPIRXEMU when the debug probe is connected. Reset type: SYSRSn SPRUH18I – JANUARY 2011 – REVISED JUNE 2022 TMS320x2806x Microcontrollers Submit Document Feedback Copyright © 2022 Texas Instruments Incorporated...
Page 790 BUF FULL Flag bit is set, the contents of this register is automatically transferred to SPIDAT, and the TX BUF FULL Flag is cleared. Writes to SPITXBUF must be left-justified. Reset type: SYSRSn TMS320x2806x Microcontrollers SPRUH18I – JANUARY 2011 – REVISED JUNE 2022 Submit Document Feedback Copyright © 2022 Texas Instruments Incorporated...
Page 792 0h (R/W) = Write 0 has no effect on TXFIFINT flag bit, Bit reads back a zero. 1h (R/W) = Write 1 to clear SPIFFTX[TXFFINT] flag. TMS320x2806x Microcontrollers SPRUH18I – JANUARY 2011 – REVISED JUNE 2022 Submit Document Feedback Copyright © 2022 Texas Instruments Incorporated...
Page 793 4h (R/W) = A TX FIFO interrupt request is generated when there are 4 words or fewer remaining in the TX buffer. 1Fh (R/W) = Reserved. SPRUH18I – JANUARY 2011 – REVISED JUNE 2022 TMS320x2806x Microcontrollers Submit Document Feedback Copyright © 2022 Texas Instruments Incorporated...
Page 794 0h (R/W) = Write 0 has no effect on RXFIFINT flag bit, Bit reads back a zero. 1h (R/W) = Write 1 to clear SPIFFRX[RXFFINT] flag TMS320x2806x Microcontrollers SPRUH18I – JANUARY 2011 – REVISED JUNE 2022 Submit Document Feedback Copyright © 2022 Texas Instruments Incorporated...
Page 795 4h (R/W) = A RX FIFO interrupt request is generated when there are 4 words in the RX buffer. 1Fh (R/W) = Reserved. SPRUH18I – JANUARY 2011 – REVISED JUNE 2022 TMS320x2806x Microcontrollers Submit Document Feedback Copyright © 2022 Texas Instruments Incorporated...
Page 796 FFh (R/W) = The next word in the TX FIFO buffer is transferred to SPITXBUF 255 serial clock cycles after completion of transmission of the previous word. TMS320x2806x Microcontrollers SPRUH18I – JANUARY 2011 – REVISED JUNE 2022 Submit Document Feedback Copyright © 2022 Texas Instruments Incorporated...
Page 797 0h (R/W) = Emulation mode is selected by the SOFT bit 1h (R/W) = Free run, continue SPI operation regardless of suspend or when the suspend occurred. RESERVED Reserved SPRUH18I – JANUARY 2011 – REVISED JUNE 2022 TMS320x2806x Microcontrollers Submit Document Feedback Copyright © 2022 Texas Instruments Incorporated...
Page 798 In slave mode, the SPISOMI pin becomes the SPISISO (slave receive and transmit) pin and SPISIMO is free for non-SPI use. TMS320x2806x Microcontrollers SPRUH18I – JANUARY 2011 – REVISED JUNE 2022 Submit Document Feedback Copyright © 2022 Texas Instruments Incorporated...
Page 799 13.9 Address-Bit Multiprocessor Mode........................13.10 SCI Communication Format..........................13.11 SCI Port Interrupts..............................810 13.12 SCI Baud Rate Calculations..........................13.13 SCI Enhanced Features............................811 13.14 SCI Registers................................ SPRUH18I – JANUARY 2011 – REVISED JUNE 2022 TMS320x2806x Microcontrollers Submit Document Feedback Copyright © 2022 Texas Instruments Incorporated...
Page 800 Separate enable bits for transmitter and receiver interrupts (except BRKDT) • NRZ (non-return-to-zero) format Enhanced features include: • Auto-baud-detect hardware logic • 4-level transmit/receive FIFO TMS320x2806x Microcontrollers SPRUH18I – JANUARY 2011 – REVISED JUNE 2022 Submit Document Feedback Copyright © 2022 Texas Instruments Incorporated...
Page 801 SCITXD SCI Asynchronous Serial Port transmit data Control Baud clock LSPCLK Prescaled clock Interrupt signals TXINT Transmit interrupt RXINT Receive Interrupt SPRUH18I – JANUARY 2011 – REVISED JUNE 2022 TMS320x2806x Microcontrollers Submit Document Feedback Copyright © 2022 Texas Instruments Incorporated...
Page 802 11b. The internal pullups can be configured in the GPyPUD register. See the General-Purpose Input/Output (GPIO) chapter for more details on GPIO mux and settings. TMS320x2806x Microcontrollers SPRUH18I – JANUARY 2011 – REVISED JUNE 2022 Submit Document Feedback Copyright © 2022 Texas Instruments Incorporated...
Page 803 Determines the number of stop bits transmitted—one stop bit if cleared to 0 or two stop bits if set to 1. SPRUH18I – JANUARY 2011 – REVISED JUNE 2022 TMS320x2806x Microcontrollers Submit Document Feedback Copyright © 2022 Texas Instruments Incorporated...
Page 804 If not, the software routine exits with the SLEEP bit still set, and does not receive interrupts until the next block start. TMS320x2806x Microcontrollers SPRUH18I – JANUARY 2011 – REVISED JUNE 2022 Submit Document Feedback Copyright © 2022 Texas Instruments Incorporated...
Page 805 (A don't care byte has to be written to SCITXBUF after setting TXWAKE, and before sending the address, so as to transmit the idle time.) SPRUH18I – JANUARY 2011 – REVISED JUNE 2022 TMS320x2806x Microcontrollers Submit Document Feedback Copyright © 2022 Texas Instruments Incorporated...
Page 806 The receiver operates regardless of the SLEEP bit. However, the receiver neither sets RXRDY nor the error status bits, nor does it request a receive interrupt until an address frame is detected. TMS320x2806x Microcontrollers SPRUH18I – JANUARY 2011 – REVISED JUNE 2022 Submit Document Feedback Copyright © 2022 Texas Instruments Incorporated...
Page 807 Idle time is of no significance Address bit Parity Stop Start Address-bit mode frame example Figure 13-6. Address-Bit Multiprocessor Communication Format SPRUH18I – JANUARY 2011 – REVISED JUNE 2022 TMS320x2806x Microcontrollers Submit Document Feedback Copyright © 2022 Texas Instruments Incorporated...
Page 808 6. Bit RXENA is brought low to disable the receiver. Data continues to be assembled in RXSHF but is not transferred to the receiver buffer register. TMS320x2806x Microcontrollers SPRUH18I – JANUARY 2011 – REVISED JUNE 2022 Submit Document Feedback Copyright © 2022 Texas Instruments Incorporated...
Page 809 6. Bit TXENA goes low to disable the transmitter; the SCI finishes transmitting the current character. 7. Transmission of the second character is complete; transmitter is empty and ready for new character. SPRUH18I – JANUARY 2011 – REVISED JUNE 2022 TMS320x2806x Microcontrollers Submit Document Feedback Copyright © 2022 Texas Instruments Incorporated...
Page 810 5207 (1457h) 2400 4800 2603 (A2Bh) 4800 9600 1301 (515h) 9601 0.01 19200 650 (28Ah) 19201 0.01 38400 324 (144h) 38462 0.16 TMS320x2806x Microcontrollers SPRUH18I – JANUARY 2011 – REVISED JUNE 2022 Submit Document Feedback Copyright © 2022 Texas Instruments Incorporated...
Page 811 SCI. Default value for these trigger level bits will be 0x11111 for receive FIFO and 0x00000 for transmit FIFO, respectively. Figure 13-10 Table 13-4 explain the operation/configuration of SCI interrupts in nonFIFO/FFO mode. SPRUH18I – JANUARY 2011 – REVISED JUNE 2022 TMS320x2806x Microcontrollers Submit Document Feedback Copyright © 2022 Texas Instruments Incorporated...
Page 812 FIFO mode TXSHF is directly loaded after delay value, TXBUF is not used. RXERR can be set by BRKDT, FE, OE, PE flags. In FIFO mode, BRKDT interrupt is only through RXERR flag. TMS320x2806x Microcontrollers SPRUH18I – JANUARY 2011 – REVISED JUNE 2022 Submit Document Feedback Copyright © 2022 Texas Instruments Incorporated...
Page 813 The host may then handshake with the loaded C28x application to set the SCI baud rate register to the desired higher baud rate. SPRUH18I – JANUARY 2011 – REVISED JUNE 2022 TMS320x2806x Microcontrollers Submit Document Feedback Copyright © 2022 Texas Instruments Incorporated...
Page 814 SCIFFRX SCI FIFO Receive Register Section 13.14.2.11 SCIFFCT SCI FIFO Control Register Section 13.14.2.12 SCIPRI SCI Priority Control Register Section 13.14.2.13 TMS320x2806x Microcontrollers SPRUH18I – JANUARY 2011 – REVISED JUNE 2022 Submit Document Feedback Copyright © 2022 Texas Instruments Incorporated...
Page 815 When this variable is used in a register name, an offset, or an address it refers to the value of a register array. SPRUH18I – JANUARY 2011 – REVISED JUNE 2022 TMS320x2806x Microcontrollers Submit Document Feedback Copyright © 2022 Texas Instruments Incorporated...
Page 816 RS-232 type communications. Reset type: SYSRSn 0h (R/W) = Idle-line mode protocol selected 1h (R/W) = Address-bit mode protocol selected TMS320x2806x Microcontrollers SPRUH18I – JANUARY 2011 – REVISED JUNE 2022 Submit Document Feedback Copyright © 2022 Texas Instruments Incorporated...
Page 817 2h (R/W) = SCICHAR_LENGTH_3 3h (R/W) = SCICHAR_LENGTH_4 4h (R/W) = SCICHAR_LENGTH_5 5h (R/W) = SCICHAR_LENGTH_6 6h (R/W) = SCICHAR_LENGTH_7 7h (R/W) = SCICHAR_LENGTH_8 SPRUH18I – JANUARY 2011 – REVISED JUNE 2022 TMS320x2806x Microcontrollers Submit Document Feedback Copyright © 2022 Texas Instruments Incorporated...
Page 818 (registers SCICTL2 and SCIRXST) to the reset condition. 1h (R/W) = After a system reset, re-enable the SCI by writing a 1 to this bit. RESERVED Reserved TMS320x2806x Microcontrollers SPRUH18I – JANUARY 2011 – REVISED JUNE 2022 Submit Document Feedback Copyright © 2022 Texas Instruments Incorporated...
Page 819 0h (R/W) = Prevent received characters from transfer into the SCIRXEMU and SCIRXBUF receiver buffers 1h (R/W) = Send received characters to SCIRXEMU and SCIRXBUF SPRUH18I – JANUARY 2011 – REVISED JUNE 2022 TMS320x2806x Microcontrollers Submit Document Feedback Copyright © 2022 Texas Instruments Incorporated...
Page 820 SCI Asynchronous Baud = LSPCLK / 16 Where: BRR = the 16-bit value (in decimal) in the baud-select registers Reset type: SYSRSn TMS320x2806x Microcontrollers SPRUH18I – JANUARY 2011 – REVISED JUNE 2022 Submit Document Feedback Copyright © 2022 Texas Instruments Incorporated...
Page 821 -empty flags. Figure 13-15. SCI Control Register 2 (SCICTL2) RESERVED R-0h TXRDY TXEMPTY RESERVED RXBKINTENA TXINTENA R-1h R-1h R-0h R/W-0h R/W-0h SPRUH18I – JANUARY 2011 – REVISED JUNE 2022 TMS320x2806x Microcontrollers Submit Document Feedback Copyright © 2022 Texas Instruments Incorporated...
Page 822 If TXINTENA is enabled after writing the data to SCITXBUF, it will not generate an interrupt. Reset type: SYSRSn 0h (R/W) = Disable TXRDY interrupt 1h (R/W) = Enable TXRDY interrupt TMS320x2806x Microcontrollers SPRUH18I – JANUARY 2011 – REVISED JUNE 2022 Submit Document Feedback Copyright © 2022 Texas Instruments Incorporated...
Page 823 SW RESET bit or by a system reset. Reset type: SYSRSn 0h (R/W) = No break condition 1h (R/W) = Break condition occurred SPRUH18I – JANUARY 2011 – REVISED JUNE 2022 TMS320x2806x Microcontrollers Submit Document Feedback Copyright © 2022 Texas Instruments Incorporated...
Page 824 - The transfer of the first byte after the address byte to SCIRXBUF (only in non-FIFO mode) - The reading of SCIRXBUF - An active SW RESET - A system reset RESERVED Reserved TMS320x2806x Microcontrollers SPRUH18I – JANUARY 2011 – REVISED JUNE 2022 Submit Document Feedback Copyright © 2022 Texas Instruments Incorporated...
Page 825 Table 13-14. SCI Receive Emulation Buffer (SCIRXEMU) Register Field Descriptions Field Type Reset Description 15-8 RESERVED Reserved ERXDT Receive emulation buffer data Reset type: SYSRSn SPRUH18I – JANUARY 2011 – REVISED JUNE 2022 TMS320x2806x Microcontrollers Submit Document Feedback Copyright © 2022 Texas Instruments Incorporated...
Page 826 7-0. This bit is associated with the character on the top of the FIFO. 13-8 RESERVED Reserved Receive Character bits Reset type: SYSRSn TMS320x2806x Microcontrollers SPRUH18I – JANUARY 2011 – REVISED JUNE 2022 Submit Document Feedback Copyright © 2022 Texas Instruments Incorporated...
Page 827 Figure 13-20. SCI FIFO Transmit (SCIFFTX) Register SCIRST SCIFFENA TXFIFORESET TXFFST R/W-1h R/W-0h R/W-1h R-0h TXFFINT TXFFINTCLR TXFFIENA TXFFIL R-0h R-0/W1S-0h R/W-0h R/W-0h SPRUH18I – JANUARY 2011 – REVISED JUNE 2022 TMS320x2806x Microcontrollers Submit Document Feedback Copyright © 2022 Texas Instruments Incorporated...
Page 828 TXFFIL to best fit their application needs by weighing between the CPU overhead to service the ISR and the best possible usage of SCI bus bandwidth. Reset type: SYSRSn TMS320x2806x Microcontrollers SPRUH18I – JANUARY 2011 – REVISED JUNE 2022 Submit Document Feedback Copyright © 2022 Texas Instruments Incorporated...
Page 829 0h (R/W) = Write 0 has no effect on RXFIFINT flag bit. Bit reads back a zero. 1h (R/W) = Write 1 to clear RXFFINT flag in bit 7 SPRUH18I – JANUARY 2011 – REVISED JUNE 2022 TMS320x2806x Microcontrollers Submit Document Feedback Copyright © 2022 Texas Instruments Incorporated...
Page 830 RXFFIL to best fit their application needs by weighing between the CPU overhead to service the ISR and the best possible usage of received SCI data. Reset type: SYSRSn TMS320x2806x Microcontrollers SPRUH18I – JANUARY 2011 – REVISED JUNE 2022 Submit Document Feedback Copyright © 2022 Texas Instruments Incorporated...
Page 831 FFTXDLY between one frame and the next frame is equal to number of baud clock cycles that FFTXDLY is set to minus 1. Reset type: SYSRSn SPRUH18I – JANUARY 2011 – REVISED JUNE 2022 TMS320x2806x Microcontrollers Submit Document Feedback Copyright © 2022 Texas Instruments Incorporated...
Page 832 1h (R/W) = Complete current receive/transmit sequence before stopping 2h (R/W) = Free run 3h (R/W) = Free run RESERVED Reserved TMS320x2806x Microcontrollers SPRUH18I – JANUARY 2011 – REVISED JUNE 2022 Submit Document Feedback Copyright © 2022 Texas Instruments Incorporated...
Page 833 14.3 I2C Module Operational Details..........................839 14.4 Interrupt Requests Generated by the I2C Module....................14.5 Resetting or Disabling the I2C Module.........................853 14.6 I2C Registers................................853 SPRUH18I – JANUARY 2011 – REVISED JUNE 2022 TMS320x2806x Microcontrollers Submit Document Feedback Copyright © 2022 Texas Instruments Incorporated...
Page 834 Expert Materials • I2C Bus Pull-Up Resistor Calculation Application Report • Maximum Clock Frequency of I2C Bus Using Repeaters Application Report TMS320x2806x Microcontrollers SPRUH18I – JANUARY 2011 – REVISED JUNE 2022 Submit Document Feedback Copyright © 2022 Texas Instruments Incorporated...
Page 835 Free data format mode 14.1.3 Features Not Supported The I2C module does not support: • High-speed mode (Hs-mode) • CBUS-compatibility mode SPRUH18I – JANUARY 2011 – REVISED JUNE 2022 TMS320x2806x Microcontrollers Submit Document Feedback Copyright © 2022 Texas Instruments Incorporated...
Page 836 I2CDXR is copied to I2CXSR and shifted out on the SDA pin one bit at a time. When the I2C module is configured as a receiver, received data is shifted into I2CRSR and then copied to I2CDRR. TMS320x2806x Microcontrollers SPRUH18I – JANUARY 2011 – REVISED JUNE 2022 Submit Document Feedback Copyright © 2022 Texas Instruments Incorporated...
Page 837 Figure 14-3. Clocking Diagram for the I2C Module Note To meet all of the I2C protocol timing specifications, the I2C module clock must be between 7-12 MHz. SPRUH18I – JANUARY 2011 – REVISED JUNE 2022 TMS320x2806x Microcontrollers Submit Document Feedback Copyright © 2022 Texas Instruments Incorporated...
Page 838 14-1. IPSC is described in the I2CPSC register. Table 14-1. Dependency of Delay d on the Divide-Down Value IPSC IPSC Greater than 1 TMS320x2806x Microcontrollers SPRUH18I – JANUARY 2011 – REVISED JUNE 2022 Submit Document Feedback Copyright © 2022 Texas Instruments Incorporated...
Page 839 If the master has requested data from the I2C module, the module must be changed to the slave-transmitter mode. SPRUH18I – JANUARY 2011 – REVISED JUNE 2022 TMS320x2806x Microcontrollers Submit Document Feedback Copyright © 2022 Texas Instruments Incorporated...
Page 840 None Reserved bit combination (No activity) S = START condition; A = Address; D = Data byte; P = STOP condition; TMS320x2806x Microcontrollers SPRUH18I – JANUARY 2011 – REVISED JUNE 2022 Submit Document Feedback Copyright © 2022 Texas Instruments Incorporated...
Page 841 Store received data in a buffer from RXFIFO (More bytes needs (More bytes needs to be transmitted) to be received) Figure 14-6. I2C Slave TX / RX Flowchart SPRUH18I – JANUARY 2011 – REVISED JUNE 2022 TMS320x2806x Microcontrollers Submit Document Feedback Copyright © 2022 Texas Instruments Incorporated...
Page 842 More bytes to be More bytes to be transmitted? received? Generate STOP condition (STP = 1) Figure 14-7. I2C Master TX / RX Flowchart TMS320x2806x Microcontrollers SPRUH18I – JANUARY 2011 – REVISED JUNE 2022 Submit Document Feedback Copyright © 2022 Texas Instruments Incorporated...
Page 843 I2C peripheral in between transfers, repeat steps 1 through 3 every time the I2C peripheral is taken out of reset. SPRUH18I – JANUARY 2011 – REVISED JUNE 2022 TMS320x2806x Microcontrollers Submit Document Feedback Copyright © 2022 Texas Instruments Incorporated...
Page 844 Once you start I2C transaction in non-repeat mode (or) repeat mode, you cannot switch into another mode until the I2C transaction is completed with a STOP condition. TMS320x2806x Microcontrollers SPRUH18I – JANUARY 2011 – REVISED JUNE 2022 Submit Document Feedback Copyright © 2022 Texas Instruments Incorporated...
Page 845 R/ W bit). n is a number from 1 to 8 determined by the bit count (BC) field of I2CMDR. After the data bits have been transferred, the receiver inserts an ACK bit. SPRUH18I – JANUARY 2011 – REVISED JUNE 2022 TMS320x2806x Microcontrollers Submit Document Feedback Copyright © 2022 Texas Instruments Incorporated...
Page 846 In master mode and free data TRX = 0: The I2C module is a receiver. format mode TRX = 1: The I2C module is a transmitter. TMS320x2806x Microcontrollers SPRUH18I – JANUARY 2011 – REVISED JUNE 2022 Submit Document Feedback Copyright © 2022 Texas Instruments Incorporated...
Page 847 SCL from device #1 SCL from device #2 Bus line Figure 14-14. Synchronization of Two I2C Clock Generators During Arbitration SPRUH18I – JANUARY 2011 – REVISED JUNE 2022 TMS320x2806x Microcontrollers Submit Document Feedback Copyright © 2022 Texas Instruments Incorporated...
Page 848 Data from device #1 Data from device #2 Bus line Device #2 drives SDA Figure 14-15. Arbitration Procedure Between Two Master-Transmitters TMS320x2806x Microcontrollers SPRUH18I – JANUARY 2011 – REVISED JUNE 2022 Submit Document Feedback Copyright © 2022 Texas Instruments Incorporated...
Page 849 Figure 14-16. Pin Diagram Showing the Effects of the Digital Loopback Mode (DLB) Bit Note The free data format (I2CMDR.FDF = 1) is not supported in digital loopback mode. SPRUH18I – JANUARY 2011 – REVISED JUNE 2022 TMS320x2806x Microcontrollers Submit Document Feedback Copyright © 2022 Texas Instruments Incorporated...
Page 850 Reset the module (IRS = 0 in I2CMDR). = 1 to generate a STOP condition Set the NACKMOD bit of I2CMDR before the rising edge of the last data bit you intend to receive TMS320x2806x Microcontrollers SPRUH18I – JANUARY 2011 – REVISED JUNE 2022 Submit Document Feedback Copyright © 2022 Texas Instruments Incorporated...
Page 851 Addressed as slave condition: The I2C has been addressed as a slave device by another master on the I2C bus. As an alternative to using AASINT, the CPU can poll the AAS bit of the status register, I2CSTR. SPRUH18I – JANUARY 2011 – REVISED JUNE 2022 TMS320x2806x Microcontrollers Submit Document Feedback Copyright © 2022 Texas Instruments Incorporated...
Page 852 The I2C module has a backwards compatibility bit (BC) in the I2CEMDR register. The timing diagram in demonstrates the effect the backwards compatibility bit has on I2C module registers and interrupts when configured as a slave-transmitter. TMS320x2806x Microcontrollers SPRUH18I – JANUARY 2011 – REVISED JUNE 2022 Submit Document Feedback Copyright © 2022 Texas Instruments Incorporated...
Page 853 14.6.1 I2C Base Address Table Table 14-7. I2C Base Address Table Bit Field Name Base Address Instance Structure I2caRegs I2C_REGS 0x0000_7900 SPRUH18I – JANUARY 2011 – REVISED JUNE 2022 TMS320x2806x Microcontrollers Submit Document Feedback Copyright © 2022 Texas Instruments Incorporated...
Page 854 I2C Extended Mode Section 14.6.2.12 I2CPSC I2C Prescaler Section 14.6.2.13 I2CFFTX I2C FIFO Transmit Section 14.6.2.14 I2CFFRX I2C FIFO Receive Section 14.6.2.15 TMS320x2806x Microcontrollers SPRUH18I – JANUARY 2011 – REVISED JUNE 2022 Submit Document Feedback Copyright © 2022 Texas Instruments Incorporated...
Page 855 When this variable is used in a register name, an offset, or an address it refers to the value of a register array. SPRUH18I – JANUARY 2011 – REVISED JUNE 2022 TMS320x2806x Microcontrollers Submit Document Feedback Copyright © 2022 Texas Instruments Incorporated...
Page 856 In 10-bit addressing mode (XA = 1 in I2CMDR): 000h-3FFh Bits 9-0 provide the 10-bit slave address of the I2C module. Reset type: SYSRSn TMS320x2806x Microcontrollers SPRUH18I – JANUARY 2011 – REVISED JUNE 2022 Submit Document Feedback Copyright © 2022 Texas Instruments Incorporated...
Page 857 1h (R/W) = Interrupt request enabled ARBL Arbitration-lost interrupt enable Reset type: SYSRSn 0h (R/W) = Interrupt request disabled 1h (R/W) = Interrupt request enabled SPRUH18I – JANUARY 2011 – REVISED JUNE 2022 TMS320x2806x Microcontrollers Submit Document Feedback Copyright © 2022 Texas Instruments Incorporated...
Page 858 - The I2C module is reset. 1h (R/W) = Bus busy: The I2C module has received or transmitted a START bit on the bus. TMS320x2806x Microcontrollers SPRUH18I – JANUARY 2011 – REVISED JUNE 2022 Submit Document Feedback Copyright © 2022 Texas Instruments Incorporated...
Page 859 - SCD is manually cleared. To clear this bit, write a 1 to it. - The I2C module is reset. 1h (R/W) = A STOP condition has been detected on the I2C bus. SPRUH18I – JANUARY 2011 – REVISED JUNE 2022 TMS320x2806x Microcontrollers Submit Document Feedback Copyright © 2022 Texas Instruments Incorporated...
Page 860 STOP condition when the counter reaches 0). In the repeat mode (RM = 1): ARDY is set at the end of each byte transmitted from I2CDXR. TMS320x2806x Microcontrollers SPRUH18I – JANUARY 2011 – REVISED JUNE 2022 Submit Document Feedback Copyright © 2022 Texas Instruments Incorporated...
Page 861 1. When AL becomes 1, the MST and STP bits of I2CMDR are cleared, and the I2C module becomes a slave-receiver. SPRUH18I – JANUARY 2011 – REVISED JUNE 2022 TMS320x2806x Microcontrollers Submit Document Feedback Copyright © 2022 Texas Instruments Incorporated...
Page 862 Introduction for details. Note: These bits must be set to a non-zero value for proper I2C clock generation. Reset type: SYSRSn TMS320x2806x Microcontrollers SPRUH18I – JANUARY 2011 – REVISED JUNE 2022 Submit Document Feedback Copyright © 2022 Texas Instruments Incorporated...
Page 863 1h (R/W) = data count value is 1 2h (R/W) = data count value is 2 FFFFh (R/W) = data count value is 65535 SPRUH18I – JANUARY 2011 – REVISED JUNE 2022 TMS320x2806x Microcontrollers Submit Document Feedback Copyright © 2022 Texas Instruments Incorporated...
Page 864 Table 14-16. I2C Data Receive Register (I2CDRR) Field Descriptions Field Type Reset Description 15-8 RESERVED Reserved DATA Receive data Reset type: SYSRSn TMS320x2806x Microcontrollers SPRUH18I – JANUARY 2011 – REVISED JUNE 2022 Submit Document Feedback Copyright © 2022 Texas Instruments Incorporated...
Page 865 000h-3FFh Bits 9-0 provide the 10-bit slave address that the I2C module transmits when it is in the master transmitter mode. Reset type: SYSRSn SPRUH18I – JANUARY 2011 – REVISED JUNE 2022 TMS320x2806x Microcontrollers Submit Document Feedback Copyright © 2022 Texas Instruments Incorporated...
Page 866 Table 14-18. I2C Data Transmit Register (I2CDXR) Field Descriptions Field Type Reset Description 15-8 RESERVED Reserved DATA Transmit data Reset type: SYSRSn TMS320x2806x Microcontrollers SPRUH18I – JANUARY 2011 – REVISED JUNE 2022 Submit Document Feedback Copyright © 2022 Texas Instruments Incorporated...
Page 867 1h (R/W) = In the master mode, setting STT to 1 causes the I2C module to generate a START condition on the I2C-bus SPRUH18I – JANUARY 2011 – REVISED JUNE 2022 TMS320x2806x Microcontrollers Submit Document Feedback Copyright © 2022 Texas Instruments Incorporated...
Page 868 The I2C module transmits 10-bit slave addresses (from bits 9-0 of I2CSAR), and its own slave address has 10 bits (bits 9-0 of I2COAR). TMS320x2806x Microcontrollers SPRUH18I – JANUARY 2011 – REVISED JUNE 2022 Submit Document Feedback Copyright © 2022 Texas Instruments Incorporated...
Page 869 3. A dummy acknowledge clock pulse 4. A repeated START condition Then, as normal, the I2C module sends the slave address that is in I2CSAR. SPRUH18I – JANUARY 2011 – REVISED JUNE 2022 TMS320x2806x Microcontrollers Submit Document Feedback Copyright © 2022 Texas Instruments Incorporated...
Page 870 5h (R/W) = 5 bits per data byte 6h (R/W) = 6 bits per data byte 7h (R/W) = 7 bits per data byte TMS320x2806x Microcontrollers SPRUH18I – JANUARY 2011 – REVISED JUNE 2022 Submit Document Feedback Copyright © 2022 Texas Instruments Incorporated...
Page 871 4h (R/W) = Receive data ready 5h (R/W) = Transmit data ready 6h (R/W) = Stop condition detected 7h (R/W) = Addressed as slave SPRUH18I – JANUARY 2011 – REVISED JUNE 2022 TMS320x2806x Microcontrollers Submit Document Feedback Copyright © 2022 Texas Instruments Incorporated...
Page 872 0h (R/W) = See the "Backwards Compatibility Mode Bit, Slave Transmitter" Figure for details. 1h (R/W) = See the "Backwards Compatibility Mode Bit, Slave Transmitter" Figure for details. TMS320x2806x Microcontrollers SPRUH18I – JANUARY 2011 – REVISED JUNE 2022 Submit Document Feedback Copyright © 2022 Texas Instruments Incorporated...
Page 873 = I2C input clock frequency/(IPSC + 1) Note: IPSC must be initialized while the I2C module is in reset (IRS = 0 in I2CMDR). Reset type: SYSRSn SPRUH18I – JANUARY 2011 – REVISED JUNE 2022 TMS320x2806x Microcontrollers Submit Document Feedback Copyright © 2022 Texas Instruments Incorporated...
Page 874 0h (R/W) = Disabled. TXFFINT flag does not generate an interrupt when set. 1h (R/W) = Enabled. TXFFINT flag does generate an interrupt when set. TMS320x2806x Microcontrollers SPRUH18I – JANUARY 2011 – REVISED JUNE 2022 Submit Document Feedback Copyright © 2022 Texas Instruments Incorporated...
Page 875 TXFFIENA bit is set. Because the I2C on this device has a 4-level transmit FIFO, these bits cannot be configured for an interrupt of more than 4 FIFO levels. Reset type: SYSRSn SPRUH18I – JANUARY 2011 – REVISED JUNE 2022 TMS320x2806x Microcontrollers Submit Document Feedback Copyright © 2022 Texas Instruments Incorporated...
Page 876 4-level receive FIFO, these bits cannot be configured for an interrupt of more than 4 FIFO levels. Reset type: SYSRSn TMS320x2806x Microcontrollers SPRUH18I – JANUARY 2011 – REVISED JUNE 2022 Submit Document Feedback Copyright © 2022 Texas Instruments Incorporated...
Page 877 15.6 SPI Operation Using the Clock Stop Mode......................15.7 Receiver Configuration............................15.8 Transmitter Configuration............................938 15.9 Emulation and Reset Considerations........................954 15.10 Data Packing Examples............................15.11 McBSP_REGS Registers............................959 SPRUH18I – JANUARY 2011 – REVISED JUNE 2022 TMS320x2806x Microcontrollers Submit Document Feedback Copyright © 2022 Texas Instruments Incorporated...
Page 878 The option of transmitting/receiving 8-bit data with the LSB first • Status bits for flagging exception/error conditions • ABIS mode is not supported. TMS320x2806x Microcontrollers SPRUH18I – JANUARY 2011 – REVISED JUNE 2022 Submit Document Feedback Copyright © 2022 Texas Instruments Incorporated...
Page 879 The McBSP consists of a data-flow path and a control path connected to external devices by six pins as shown Figure 15-1. The figure and the text in this section use generic pin names. SPRUH18I – JANUARY 2011 – REVISED JUNE 2022 TMS320x2806x Microcontrollers Submit Document Feedback Copyright © 2022 Texas Instruments Incorporated...
Page 880 The use of registers varies, depending on whether the defined length of each serial word is 16 bits. TMS320x2806x Microcontrollers SPRUH18I – JANUARY 2011 – REVISED JUNE 2022 Submit Document Feedback Copyright © 2022 Texas Instruments Incorporated...
Page 881 8-bit wide serial data stream. If companding is enabled and either of the frame phases does not have an 8-bit word length, companding continues as if the word length is 8 bits. SPRUH18I – JANUARY 2011 – REVISED JUNE 2022 TMS320x2806x Microcontrollers Submit Document Feedback Copyright © 2022 Texas Instruments Incorporated...
Page 882 The McBSP is enabled in digital loopback mode with companding appropriately enabled by RCOMPAND and XCOMPAND. Receive and transmit interrupts (RINT when RINTM = 0 and XINT when XINTM = 0) or TMS320x2806x Microcontrollers SPRUH18I – JANUARY 2011 – REVISED JUNE 2022 Submit Document Feedback Copyright © 2022 Texas Instruments Incorporated...
Page 883 During transmission, XSR does not accept new data from DXR until a full serial word has been passed from XSR to the DX pin. SPRUH18I – JANUARY 2011 – REVISED JUNE 2022 TMS320x2806x Microcontrollers Submit Document Feedback Copyright © 2022 Texas Instruments Incorporated...
Page 884 Unexpected Transmit Frame-Synchronization Pulse (see Section 15.4.5) You can also use the frame-synchronization ignore function for data packing (for more details, see Section 15.10.2). TMS320x2806x Microcontrollers SPRUH18I – JANUARY 2011 – REVISED JUNE 2022 Submit Document Feedback Copyright © 2022 Texas Instruments Incorporated...
Page 885 (XCR1 and XCR2) determine the number of phases per frame, the number of words per frame, and number of bits per word for each phase, for the receiver and transmitter. The maximum number of words per SPRUH18I – JANUARY 2011 – REVISED JUNE 2022 TMS320x2806x Microcontrollers Submit Document Feedback Copyright © 2022 Texas Instruments Incorporated...
Page 886 Notice that words, not individual bits, are shown on the D(R/X) signal. The first phase (P1) consists of a single 16-bit word. The second phase (P2) consists of twelve 20-bit words. The phase configurations are listed after the figure. TMS320x2806x Microcontrollers SPRUH18I – JANUARY 2011 – REVISED JUNE 2022 Submit Document Feedback Copyright © 2022 Texas Instruments Incorporated...
Page 887 RBR[1,2]: Receive buffer registers 1 and 2 DRR[1,2]: Data receive registers 1 and 2 Figure 15-13. McBSP Reception Physical Data Path SPRUH18I – JANUARY 2011 – REVISED JUNE 2022 TMS320x2806x Microcontrollers Submit Document Feedback Copyright © 2022 Texas Instruments Incorporated...
Page 888 This section explains the fundamental process of transmission in the McBSP. For details about how to program the McBSP transmitter, see Section 15.8. TMS320x2806x Microcontrollers SPRUH18I – JANUARY 2011 – REVISED JUNE 2022 Submit Document Feedback Copyright © 2022 Texas Instruments Incorporated...
Page 889 When activity is not properly timed, errors can occur. See the following topics for more details: • Overwrite in the Transmitter (Section 15.4.4) • Underflow in the Transmitter (Section 15.4.4.3) SPRUH18I – JANUARY 2011 – REVISED JUNE 2022 TMS320x2806x Microcontrollers Submit Document Feedback Copyright © 2022 Texas Instruments Incorporated...
Page 890 The source clock for the sample rate generator (labeled CLKSRG in the diagram) can be supplied by the LSPCLK, or by an external pin (MCLKX or MCLKR). The source is selected with the SCLKME bit of PCR and TMS320x2806x Microcontrollers SPRUH18I – JANUARY 2011 – REVISED JUNE 2022 Submit Document Feedback Copyright © 2022 Texas Instruments Incorporated...
Page 891 15-5). When CLKSM = 1, the minimum divide down value in CLKGDV bits is 1. CLKGDV is described in Section 15.3.1.4. SPRUH18I – JANUARY 2011 – REVISED JUNE 2022 TMS320x2806x Microcontrollers Submit Document Feedback Copyright © 2022 Texas Instruments Incorporated...
Page 892 0, the CLKG duty cycle is 50%. When CLKGDV is an even value, 2p, representing an odd divide down, the high-state duration is p+1 cycles and the low-state duration is p cycles. TMS320x2806x Microcontrollers SPRUH18I – JANUARY 2011 – REVISED JUNE 2022 Submit Document Feedback Copyright © 2022 Texas Instruments Incorporated...
Page 893 GSYNC bit of SRGR2 and the FSR pin can be used to control the timing of CLKG and the pulsing of FSG relative to the chosen input clock. SPRUH18I – JANUARY 2011 – REVISED JUNE 2022 TMS320x2806x Microcontrollers Submit Document Feedback Copyright © 2022 Texas Instruments Incorporated...
Page 894 (No need to resynchronize) CLKG (Needs resynchronization) Figure 15-19. CLKG Synchronization and FSG Generation When GSYNC = 1 and CLKGDV = 1 TMS320x2806x Microcontrollers SPRUH18I – JANUARY 2011 – REVISED JUNE 2022 Submit Document Feedback Copyright © 2022 Texas Instruments Incorporated...
Page 895 4. If necessary, enable the receiver and the transmitter. If necessary, remove the receiver and transmitter from reset by setting RRST and/or XRST = 1. SPRUH18I – JANUARY 2011 – REVISED JUNE 2022 TMS320x2806x Microcontrollers Submit Document Feedback Copyright © 2022 Texas Instruments Incorporated...
Page 896 If new data has been written to the DXRs since the last DXR-to-XSR copy, the current value in the XSRs is lost. For more details about transmit frame-synchronization errors, see Section 15.4.5. TMS320x2806x Microcontrollers SPRUH18I – JANUARY 2011 – REVISED JUNE 2022 Submit Document Feedback Copyright © 2022 Texas Instruments Incorporated...
Page 897 DRR1 at least 2.5 cycles before the next serial word ©) is completely shifted into RSR1. This ensures that an RBR1-to-DRR1 copy of word B occurs before receiver attempts to transfer word C from RSR1 to RBR1. SPRUH18I – JANUARY 2011 – REVISED JUNE 2022 TMS320x2806x Microcontrollers Submit Document Feedback Copyright © 2022 Texas Instruments Incorporated...
Page 898 Case 1: Unexpected internal FSR pulses with RFIG = 1 in RCR2. Receive frame-synchronization pulses are ignored, and the reception continues. TMS320x2806x Microcontrollers SPRUH18I – JANUARY 2011 – REVISED JUNE 2022 Submit Document Feedback Copyright © 2022 Texas Instruments Incorporated...
Page 899 Figure 15-25 shows when a new frame-synchronization pulse on FSR can safely occur relative to the last bit of the current frame. SPRUH18I – JANUARY 2011 – REVISED JUNE 2022 TMS320x2806x Microcontrollers Submit Document Feedback Copyright © 2022 Texas Instruments Incorporated...
Page 900 Poll for XRDY = 1 in SPCR2 before writing to the DXR(s). XRDY is set when data is copied from DXR1 to XSR1 and is cleared when new data is written to DXR1. TMS320x2806x Microcontrollers SPRUH18I – JANUARY 2011 – REVISED JUNE 2022 Submit Document Feedback Copyright © 2022 Texas Instruments Incorporated...
Page 901 B is transmitted, C is written to DXR1 before the next frame-synchronization pulse. As a result, there is no underflow; B is not transmitted twice. SPRUH18I – JANUARY 2011 – REVISED JUNE 2022 TMS320x2806x Microcontrollers Submit Document Feedback Copyright © 2022 Texas Instruments Incorporated...
Page 902 Case 1: Unexpected internal FSX pulses with XFIG = 1 in XCR2. Transmit frame-synchronization pulses are ignored, and the transmission continues. TMS320x2806x Microcontrollers SPRUH18I – JANUARY 2011 – REVISED JUNE 2022 Submit Document Feedback Copyright © 2022 Texas Instruments Incorporated...
Page 903 Figure 15-31 shows when a new frame-synchronization pulse on FSX can safely occur relative to the last bit of the current frame. SPRUH18I – JANUARY 2011 – REVISED JUNE 2022 TMS320x2806x Microcontrollers Submit Document Feedback Copyright © 2022 Texas Instruments Incorporated...
Page 904 16 - 31 32 - 47 48 - 63 64 - 79 80 - 95 96 - 111 112 - 127 TMS320x2806x Microcontrollers SPRUH18I – JANUARY 2011 – REVISED JUNE 2022 Submit Document Feedback Copyright © 2022 Texas Instruments Incorporated...
Page 905 B and A until the complete frame has been transferred. When the next frame-synchronization pulse occurs, the next frame is transferred beginning with the channels in partition A. SPRUH18I – JANUARY 2011 – REVISED JUNE 2022 TMS320x2806x Microcontrollers Submit Document Feedback Copyright © 2022 Texas Instruments Incorporated...
Page 906 (R/X)PABLK to assign different channels to partition A nor (R/X)CERA to change the channel configuration for partition A. TMS320x2806x Microcontrollers SPRUH18I – JANUARY 2011 – REVISED JUNE 2022 Submit Document Feedback Copyright © 2022 Texas Instruments Incorporated...
Page 907 Block 5: channels 80 through 95 RCERF Block 6: channels 96 through 111 RCERG Block 7: channels 112 through 127 RCERH SPRUH18I – JANUARY 2011 – REVISED JUNE 2022 TMS320x2806x Microcontrollers Submit Document Feedback Copyright © 2022 Texas Instruments Incorporated...
Page 908 3. Accepts bits shifted in from the DR pin in channel 15 4. Ignores bits received in channels 16-38 5. Accepts bits shifted in from the DR pin in channel 39 TMS320x2806x Microcontrollers SPRUH18I – JANUARY 2011 – REVISED JUNE 2022 Submit Document Feedback Copyright © 2022 Texas Instruments Incorporated...
Page 909 4. Places the DX pin in the high impedance state in channels 16-38 5. Shifts data to the DX pin in channel 39 SPRUH18I – JANUARY 2011 – REVISED JUNE 2022 TMS320x2806x Microcontrollers Submit Document Feedback Copyright © 2022 Texas Instruments Incorporated...
Page 910 Section 15.5.4) and you want to know when you can assign a different block of channels to partition A or B. TMS320x2806x Microcontrollers SPRUH18I – JANUARY 2011 – REVISED JUNE 2022 Submit Document Feedback Copyright © 2022 Texas Instruments Incorporated...
Page 911 DXR1 to XSR1 copy (W3) DXR1 to XSR1 copy (W1) Figure 15-35. Activity on McBSP Pins for the Possible Values of XMCM SPRUH18I – JANUARY 2011 – REVISED JUNE 2022 TMS320x2806x Microcontrollers Submit Document Feedback Copyright © 2022 Texas Instruments Incorporated...
Page 912 The receive clock signal (MCLKR) and receive frame-synchronization signal (FSR) are not used in the clock stop mode because these signals are internally connected to their transmit counterparts, CLKX and FSX. TMS320x2806x Microcontrollers SPRUH18I – JANUARY 2011 – REVISED JUNE 2022 Submit Document Feedback Copyright © 2022 Texas Instruments Incorporated...
Page 913 High inactive state with delay: The McBSP transmits data one-half cycle ahead of the falling edge of CLKX and receives data on the falling edge of MCLKR. CLKXP = 1 CLKRP = 1 SPRUH18I – JANUARY 2011 – REVISED JUNE 2022 TMS320x2806x Microcontrollers Submit Document Feedback Copyright © 2022 Texas Instruments Incorporated...
Page 914 If the McBSP is the SPI master (CLKXM = 1), SOMI = DR. If the McBSP is the SPI slave (CLKXM = 0), SOMI = DX. Figure 15-38. SPI Transfer With CLKSTP = 11b (Clock Delay), CLKXP = 0, CLKRP = 1 TMS320x2806x Microcontrollers SPRUH18I – JANUARY 2011 – REVISED JUNE 2022 Submit Document Feedback Copyright © 2022 Texas Instruments Incorporated...
Page 915 If the McBSP is the SPI master (CLKXM = 1), SOMI=DR. If the McBSP is the SPI slave (CLKXM = 0), SOMI = DX. Figure 15-40. SPI Transfer With CLKSTP = 11b (Clock Delay), CLKXP = 1, CLKRP = 1 SPRUH18I – JANUARY 2011 – REVISED JUNE 2022 TMS320x2806x Microcontrollers Submit Document Feedback Copyright © 2022 Texas Instruments Incorporated...
Page 916 After the required data acquisition setup is done (DXR[1,2] is loaded with data), set FRST = 1 if an internally generated frame-synchronization pulse is required (that is, if the McBSP is the SPI master). TMS320x2806x Microcontrollers SPRUH18I – JANUARY 2011 – REVISED JUNE 2022 Submit Document Feedback Copyright © 2022 Texas Instruments Incorporated...
Page 917 The data delay parameters of the McBSP (XDATDLY and RDATDLY) must be set to 1 for proper SPI master operation. A data delay value of 0 or 2 is undefined in the clock stop mode. SPRUH18I – JANUARY 2011 – REVISED JUNE 2022 TMS320x2806x Microcontrollers Submit Document Feedback Copyright © 2022 Texas Instruments Incorporated...
Page 918 When the McBSP is used as an SPI slave, the master clock and slave-enable signals are generated externally by a master device. Accordingly, the CLKX and FSX pins must be configured as inputs. The MCLKX pin is TMS320x2806x Microcontrollers SPRUH18I – JANUARY 2011 – REVISED JUNE 2022 Submit Document Feedback Copyright © 2022 Texas Instruments Incorporated...
Page 919 – Set the SRG clock synchronization mode. – Set the SRG clock mode (choose an input clock). – Set the SRG input clock polarity. SPRUH18I – JANUARY 2011 – REVISED JUNE 2022 TMS320x2806x Microcontrollers Submit Document Feedback Copyright © 2022 Texas Instruments Incorporated...
Page 920 In addition to this, bits 12 and 13 of the PCR register must be set to 0. These bits are defined as reserved. TMS320x2806x Microcontrollers SPRUH18I – JANUARY 2011 – REVISED JUNE 2022 Submit Document Feedback Copyright © 2022 Texas Instruments Incorporated...
Page 922 Receive phase number Specifies whether the receive frame has 1 or 2 phases. RPHASE = 0 Single-phase frame RPHASE = 1 Dual-phase frame TMS320x2806x Microcontrollers SPRUH18I – JANUARY 2011 – REVISED JUNE 2022 Submit Document Feedback Copyright © 2022 Texas Instruments Incorporated...
Page 923 1 word in phase 1 RFRLEN1 = 000 0001 2 words in phase 1 RFRLEN1 = 111 1111 128 words in phase 1 SPRUH18I – JANUARY 2011 – REVISED JUNE 2022 TMS320x2806x Microcontrollers Submit Document Feedback Copyright © 2022 Texas Instruments Incorporated...
Page 924 1. Aborts the current data transfer 2. Sets RSYNCERR in SPCR1 to 1 3. Begins the transfer of a new data word TMS320x2806x Microcontrollers SPRUH18I – JANUARY 2011 – REVISED JUNE 2022 Submit Document Feedback Copyright © 2022 Texas Instruments Incorporated...
Page 925 15.7.11.4). RCOMPAND = 10 μ-law companding, 8-bit data, MSB received first RCOMPAND = 11 A-law companding, 8-bit data, MSB received first SPRUH18I – JANUARY 2011 – REVISED JUNE 2022 TMS320x2806x Microcontrollers Submit Document Feedback Copyright © 2022 Texas Instruments Incorporated...
Page 926 Receive data delay RDATDLY = 00 0-bit data delay RDATDLY = 01 1-bit data delay RDATDLY = 10 2-bit data delay TMS320x2806x Microcontrollers SPRUH18I – JANUARY 2011 – REVISED JUNE 2022 Submit Document Feedback Copyright © 2022 Texas Instruments Incorporated...
Page 927 Figure 15-47. In this figure, the data transferred is an 8-bit value with bits labeled B7, B6, B5, and so on. SPRUH18I – JANUARY 2011 – REVISED JUNE 2022 TMS320x2806x Microcontrollers Submit Document Feedback Copyright © 2022 Texas Instruments Incorporated...
Page 928 Zero fill MSBs 000Ah BCDEh Right Sign extend data into MSBs FFFAh BCDEh Left Zero fill LSBs ABCDh E000h Reserved Reserved Reserved Reserved TMS320x2806x Microcontrollers SPRUH18I – JANUARY 2011 – REVISED JUNE 2022 Submit Document Feedback Copyright © 2022 Texas Instruments Incorporated...
Page 929 Regardless of the value of RINTM, RSYNCERR can be read to detect this condition. For information on using RSYNCERR, see Section 15.4.3. SPRUH18I – JANUARY 2011 – REVISED JUNE 2022 TMS320x2806x Microcontrollers Submit Document Feedback Copyright © 2022 Texas Instruments Incorporated...
Page 930 The internal receive clock signal (MCLKR) and the internal receive frame-synchronization signal (FSR) are internally connected to their transmit counterparts, CLKX and FSX. TMS320x2806x Microcontrollers SPRUH18I – JANUARY 2011 – REVISED JUNE 2022 Submit Document Feedback Copyright © 2022 Texas Instruments Incorporated...
Page 931 Output. Receive (same as transmit) frame synchronization is inverted as determined by FSRP before being driven out on the FSR pin. SPRUH18I – JANUARY 2011 – REVISED JUNE 2022 TMS320x2806x Microcontrollers Submit Document Feedback Copyright © 2022 Texas Instruments Incorporated...
Page 932 McBSP receiver on the falling edge of the same clock. TMS320x2806x Microcontrollers SPRUH18I – JANUARY 2011 – REVISED JUNE 2022 Submit Document Feedback Copyright © 2022 Texas Instruments Incorporated...
Page 933 When the sample rate generator comes out of reset, FSG is in its inactive state. Then, when GRST = 1 and FSGM = 1, a frame-synchronization pulse is generated. The frame width value (FWID + 1) is counted down on SPRUH18I – JANUARY 2011 – REVISED JUNE 2022 TMS320x2806x Microcontrollers Submit Document Feedback Copyright © 2022 Texas Instruments Incorporated...
Page 934 Also, in the clock stop mode, the internal receive clock signal (MCLKR) and the internal receive frame- synchronization signal (FSR) are internally connected to their transmit counterparts, CLKX and FSX. TMS320x2806x Microcontrollers SPRUH18I – JANUARY 2011 – REVISED JUNE 2022 Submit Document Feedback Copyright © 2022 Texas Instruments Incorporated...
Page 935 The receive clock polarity bit, CLKRP, sets the edge used to sample received data. The receive data is always sampled on the falling edge of internal MCLKR. Therefore, if CLKRP = 1 and external clocking is selected SPRUH18I – JANUARY 2011 – REVISED JUNE 2022 TMS320x2806x Microcontrollers Submit Document Feedback Copyright © 2022 Texas Instruments Incorporated...
Page 936 0, the CLKG duty cycle is 50%. When CLKGDV is an even value, 2p, representing an odd divide-down, the high-state duration is p + 1 cycles and the low-state duration is p cycles. TMS320x2806x Microcontrollers SPRUH18I – JANUARY 2011 – REVISED JUNE 2022 Submit Document Feedback Copyright © 2022 Texas Instruments Incorporated...
Page 937 CLKG is derived from an input clock. Table 15-45 shows the four possible sources of the input clock. For more details on generating CLKG, see Section 15.3.1.1. SPRUH18I – JANUARY 2011 – REVISED JUNE 2022 TMS320x2806x Microcontrollers Submit Document Feedback Copyright © 2022 Texas Instruments Incorporated...
Page 938 – Set the transmit DXENA mode. – Set the transmit interrupt mode. • Frame-synchronization behavior: – Set the transmit frame-synchronization mode. TMS320x2806x Microcontrollers SPRUH18I – JANUARY 2011 – REVISED JUNE 2022 Submit Document Feedback Copyright © 2022 Texas Instruments Incorporated...
Page 939 DMA PERINTFLG is edge-sensitive and will fail to recognize the XRDY, which is continuously high. For more details about McBSP reset conditions and effects, see Section 15.9.2. SPRUH18I – JANUARY 2011 – REVISED JUNE 2022 TMS320x2806x Microcontrollers Submit Document Feedback Copyright © 2022 Texas Instruments Incorporated...
Page 941 (XCERs). The XMCME bit determines whether 32 channels or 128 channels are selectable in RCERs and XCERs. SPRUH18I – JANUARY 2011 – REVISED JUNE 2022 TMS320x2806x Microcontrollers Submit Document Feedback Copyright © 2022 Texas Instruments Incorporated...
Page 942 XWDLEN1 determines the length of the serial words in phase 1 of the frame, and XWDLEN2 determines the word length in phase 2 of the frame. TMS320x2806x Microcontrollers SPRUH18I – JANUARY 2011 – REVISED JUNE 2022 Submit Document Feedback Copyright © 2022 Texas Instruments Incorporated...
Page 943 (XFRLEN1 + 1) words 0 ≤ XFRLEN1 ≤ 127 0 ≤ XFRLEN2 ≤ 127 (XFRLEN1 + 1) + (XFRLEN2 + 1) words SPRUH18I – JANUARY 2011 – REVISED JUNE 2022 TMS320x2806x Microcontrollers Submit Document Feedback Copyright © 2022 Texas Instruments Incorporated...
Page 944 (when (R/X)FIG = 1). Here, the transfer of word B is not affected by an unexpected frame-synchronization pulse. CLK(R/X) Frame synchronization ignored FS(R/X) D(R/X) (R/X)SYNCERR Figure 15-52. Unexpected Frame-Synchronization Pulse With (R/X) FIG = 1 TMS320x2806x Microcontrollers SPRUH18I – JANUARY 2011 – REVISED JUNE 2022 Submit Document Feedback Copyright © 2022 Texas Instruments Incorporated...
Page 945 0s as shown in Figure 15-54. 15-2 µ-law format in DXR1 Value Figure 15-54. μ-Law Transmit Data Companding Format SPRUH18I – JANUARY 2011 – REVISED JUNE 2022 TMS320x2806x Microcontrollers Submit Document Feedback Copyright © 2022 Texas Instruments Incorporated...
Page 946 Data delay 0 1-bit delay D(R/X) Data delay 1 2-bit delay D(R/X) Data delay 2 Figure 15-56. Range of Programmable Data Delay TMS320x2806x Microcontrollers SPRUH18I – JANUARY 2011 – REVISED JUNE 2022 Submit Document Feedback Copyright © 2022 Texas Instruments Incorporated...
Page 947 8-bit value with bits labeled B7, B6, B5, and so on. CLKR 2-bit delay Framing bit Figure 15-57. 2-Bit Data Delay Used to Skip a Framing Bit SPRUH18I – JANUARY 2011 – REVISED JUNE 2022 TMS320x2806x Microcontrollers Submit Document Feedback Copyright © 2022 Texas Instruments Incorporated...
Page 948 Regardless of the value of XINTM, XSYNCERR can be read to detect this condition. For more information on using XSYNCERR, see Section 15.4.5. TMS320x2806x Microcontrollers SPRUH18I – JANUARY 2011 – REVISED JUNE 2022 Submit Document Feedback Copyright © 2022 Texas Instruments Incorporated...
Page 949 If the McBSP is a slave, make sure that FSXM = 0 so that the McBSP can receive the slave-enable signal on the FSX pin. SPRUH18I – JANUARY 2011 – REVISED JUNE 2022 TMS320x2806x Microcontrollers Submit Document Feedback Copyright © 2022 Texas Instruments Incorporated...
Page 950 McBSP receiver on the falling edge of the same clock. TMS320x2806x Microcontrollers SPRUH18I – JANUARY 2011 – REVISED JUNE 2022 Submit Document Feedback Copyright © 2022 Texas Instruments Incorporated...
Page 951 CLKG cycle until it reaches 0, at which time FSG goes low. At the same time, the frame period value (FPER + 1) is also counting down. When this value reaches 0, FSG goes high, indicating a new frame. SPRUH18I – JANUARY 2011 – REVISED JUNE 2022 TMS320x2806x Microcontrollers Submit Document Feedback Copyright © 2022 Texas Instruments Incorporated...
Page 952 CLK(R/X) pins or driven by the sample rate generator clock (CLKG) internal to the McBSP. TMS320x2806x Microcontrollers SPRUH18I – JANUARY 2011 – REVISED JUNE 2022 Submit Document Feedback Copyright © 2022 Texas Instruments Incorporated...
Page 953 Data hold Figure 15-60. Data Clocked Externally Using a Rising Edge and Sampled by the McBSP Receiver on a Falling Edge SPRUH18I – JANUARY 2011 – REVISED JUNE 2022 TMS320x2806x Microcontrollers Submit Document Feedback Copyright © 2022 Texas Instruments Incorporated...
Page 954 Device reset. When the whole DSP is reset (XRS signal is driven low), all McBSP pins are in GPIO mode. When the device is pulled out of reset, the clock to the McBSP modules remains disabled. TMS320x2806x Microcontrollers SPRUH18I – JANUARY 2011 – REVISED JUNE 2022 Submit Document Feedback Copyright © 2022 Texas Instruments Incorporated...
Page 955 4. The bits of the channel control registers—MCR[1,2], RCER[A-H], XCER[A-H]—can be modified at any time as long as they are not being used by the current reception/transmission in a multichannel selection mode. SPRUH18I – JANUARY 2011 – REVISED JUNE 2022 TMS320x2806x Microcontrollers Submit Document Feedback Copyright © 2022 Texas Instruments Incorporated...
Page 956 DXR1 to XSR1 copy DXR1 to XSR1 copy DXR1 to XSR1 copy Figure 15-61. Four 8-Bit Data Words Transferred To/From the McBSP TMS320x2806x Microcontrollers SPRUH18I – JANUARY 2011 – REVISED JUNE 2022 Submit Document Feedback Copyright © 2022 Texas Instruments Incorporated...
Page 957 RBR1 to DRR1 copy CLKX DXR2 to XSR2 copy DXR1 to XSR1 copy Figure 15-62. One 32-Bit Data Word Transferred To/From the McBSP SPRUH18I – JANUARY 2011 – REVISED JUNE 2022 TMS320x2806x Microcontrollers Submit Document Feedback Copyright © 2022 Texas Instruments Incorporated...
Page 958 DXR2 to XSR2 copy DXR1 to XSR1 copy Figure 15-64. Configuring the Data Stream of Figure 15-63 as a Continuous 32-Bit Word TMS320x2806x Microcontrollers SPRUH18I – JANUARY 2011 – REVISED JUNE 2022 Submit Document Feedback Copyright © 2022 Texas Instruments Incorporated...
Page 959 RCERH Receive channel enable partition H XCERG Transmit channel enable partition G XCERH Transmit channel enable partition H MFFINT Interrupt enable SPRUH18I – JANUARY 2011 – REVISED JUNE 2022 TMS320x2806x Microcontrollers Submit Document Feedback Copyright © 2022 Texas Instruments Incorporated...
Page 960 When this variable is used in a register name, an offset, or an address it refers to the value of a register array. TMS320x2806x Microcontrollers SPRUH18I – JANUARY 2011 – REVISED JUNE 2022 Submit Document Feedback Copyright © 2022 Texas Instruments Incorporated...
Page 961 Table 15-74. DRR1 Register Field Descriptions Field Type Reset Description 15-8 LWHB Low-word high-byte Reset type: SYSRSn LWLB Low-word low-byte Reset type: SYSRSn SPRUH18I – JANUARY 2011 – REVISED JUNE 2022 TMS320x2806x Microcontrollers Submit Document Feedback Copyright © 2022 Texas Instruments Incorporated...
Page 962 Table 15-76. DXR1 Register Field Descriptions Field Type Reset Description 15-8 LWHB Low-word high-byte Reset type: SYSRSn LWLB Low-word low-byte Reset type: SYSRSn TMS320x2806x Microcontrollers SPRUH18I – JANUARY 2011 – REVISED JUNE 2022 Submit Document Feedback Copyright © 2022 Texas Instruments Incorporated...
Page 963 (GRST = 1), the frame-synchronization logic generates the frame-synchronization signal FSG as programmed. SPRUH18I – JANUARY 2011 – REVISED JUNE 2022 TMS320x2806x Microcontrollers Submit Document Feedback Copyright © 2022 Texas Instruments Incorporated...
Page 964 The flag remains set until you write a 0 to it or reset the transmitter. Reset type: SYSRSn 0h (R/W) = No error 1h (R/W) = Transmit frame-synchronization error TMS320x2806x Microcontrollers SPRUH18I – JANUARY 2011 – REVISED JUNE 2022 Submit Document Feedback Copyright © 2022 Texas Instruments Incorporated...
Page 965 1h (R/W) = If you read a 1, the transmitter is enabled. If you write a 1, you enable the transmitter by taking it out of its reset state. SPRUH18I – JANUARY 2011 – REVISED JUNE 2022 TMS320x2806x Microcontrollers Submit Document Feedback Copyright © 2022 Texas Instruments Incorporated...
Page 966 1h (R/W) = Right justify the data and sign-extend the data into the MSBs 2h (R/W) = Left justify the data and zero fill the LSBs 3h (R/W) = Reserved (do not use) TMS320x2806x Microcontrollers SPRUH18I – JANUARY 2011 – REVISED JUNE 2022 Submit Document Feedback Copyright © 2022 Texas Instruments Incorporated...
Page 967 RSYNCERR bit is set, indicating a receive frame-synchronization error. Regardless of the value of RINTM, you can check RSYNCERR to determine whether a receive frame-synchronization error occurred. SPRUH18I – JANUARY 2011 – REVISED JUNE 2022 TMS320x2806x Microcontrollers Submit Document Feedback Copyright © 2022 Texas Instruments Incorporated...
Page 968 1h (R/W) = If you read a 1, the receiver is enabled. If you write a 1, you enable the receiver by taking it out of its reset state. TMS320x2806x Microcontrollers SPRUH18I – JANUARY 2011 – REVISED JUNE 2022 Submit Document Feedback Copyright © 2022 Texas Instruments Incorporated...
Page 969 For example, if you want a phase length of 128 words in phase 2, load 127 into RFRLEN2. Reset type: SYSRSn SPRUH18I – JANUARY 2011 – REVISED JUNE 2022 TMS320x2806x Microcontrollers Submit Document Feedback Copyright © 2022 Texas Instruments Incorporated...
Page 970 0h (R/W) = 0-bit data delay 1h (R/W) = 1-bit data delay 2h (R/W) = 2-bit data delay 3h (R/W) = Reserved (do not use) TMS320x2806x Microcontrollers SPRUH18I – JANUARY 2011 – REVISED JUNE 2022 Submit Document Feedback Copyright © 2022 Texas Instruments Incorporated...
Page 971 5h (R/W) = 32 bits 6h (R/W) = Reserved (do not use) 7h (R/W) = Reserved (do not use) RESERVED Reserved SPRUH18I – JANUARY 2011 – REVISED JUNE 2022 TMS320x2806x Microcontrollers Submit Document Feedback Copyright © 2022 Texas Instruments Incorporated...
Page 972 For example, if you want a phase length of 128 words in phase 1, load 127 into XFRLEN1. Reset type: SYSRSn TMS320x2806x Microcontrollers SPRUH18I – JANUARY 2011 – REVISED JUNE 2022 Submit Document Feedback Copyright © 2022 Texas Instruments Incorporated...
Page 973 0h (R/W) = 0-bit data delay 1h (R/W) = 1-bit data delay 2h (R/W) = 2-bit data delay 3h (R/W) = Reserved (do not use) SPRUH18I – JANUARY 2011 – REVISED JUNE 2022 TMS320x2806x Microcontrollers Submit Document Feedback Copyright © 2022 Texas Instruments Incorporated...
Page 974 5h (R/W) = 32 bits 6h (R/W) = Reserved (do not use) 7h (R/W) = Reserved (do not use) RESERVED Reserved TMS320x2806x Microcontrollers SPRUH18I – JANUARY 2011 – REVISED JUNE 2022 Submit Document Feedback Copyright © 2022 Texas Instruments Incorporated...
Page 975 - FSG pulses. FSG only pulses in response to a pulse on the FSR pin. The frame-synchronization period defined in FPER is ignored. RESERVED Reserved SPRUH18I – JANUARY 2011 – REVISED JUNE 2022 TMS320x2806x Microcontrollers Submit Document Feedback Copyright © 2022 Texas Instruments Incorporated...
Page 976 FSG is (FPER + 1) CLKG cycles. The 12 bits of FPER allow a frame-synchronization period of 1 to 4096 CLKG cycles: Reset type: SYSRSn TMS320x2806x Microcontrollers SPRUH18I – JANUARY 2011 – REVISED JUNE 2022 Submit Document Feedback Copyright © 2022 Texas Instruments Incorporated...
Page 977 1 <= (FWID + 1) <= 256 CLKG cycles The period between the frame-synchronization pulses on FSG is defined by the FPER bits. Reset type: SYSRSn SPRUH18I – JANUARY 2011 – REVISED JUNE 2022 TMS320x2806x Microcontrollers Submit Document Feedback Copyright © 2022 Texas Instruments Incorporated...
Page 978 1h (R/W) = Block 3: channels 48 through 63 2h (R/W) = Block 5: channels 80 through 95 3h (R/W) = Block 7: channels 112 through 127 TMS320x2806x Microcontrollers SPRUH18I – JANUARY 2011 – REVISED JUNE 2022 Submit Document Feedback Copyright © 2022 Texas Instruments Incorporated...
Page 979 (XCERs). The XMCME bit determines whether 32 channels or 128 channels are selectable in RCERs and XCERs. SPRUH18I – JANUARY 2011 – REVISED JUNE 2022 TMS320x2806x Microcontrollers Submit Document Feedback Copyright © 2022 Texas Instruments Incorporated...
Page 980 RCERD: Channels 48 through 63 RCERE: Channels 64 through 79 RCERF: Channels 80 through 95 RCERG: Channels 96 through 111 RCERH: Channels 112 through 127 TMS320x2806x Microcontrollers SPRUH18I – JANUARY 2011 – REVISED JUNE 2022 Submit Document Feedback Copyright © 2022 Texas Instruments Incorporated...
Page 981 5h (R/W) = Block 5: channels 80 through 95 6h (R/W) = Block 6: channels 96 through 111 7h (R/W) = Block 7: channels 112 through 127 RESERVED Reserved SPRUH18I – JANUARY 2011 – REVISED JUNE 2022 TMS320x2806x Microcontrollers Submit Document Feedback Copyright © 2022 Texas Instruments Incorporated...
Page 982 RCERs depends on the number of receive channel partitions (2 or 8), as defined by the RMCME bit. TMS320x2806x Microcontrollers SPRUH18I – JANUARY 2011 – REVISED JUNE 2022 Submit Document Feedback Copyright © 2022 Texas Instruments Incorporated...
Page 983 0h (R/W) = Disable the channel that is mapped to RCEx. 1h (R/W) = Enable the channel that is mapped to RCEx. SPRUH18I – JANUARY 2011 – REVISED JUNE 2022 TMS320x2806x Microcontrollers Submit Document Feedback Copyright © 2022 Texas Instruments Incorporated...
Page 984 Unmask the channel that is mapped to XCEx. If the channel is also enabled by the corresponding receive channel enable bit, full transmission can occur. TMS320x2806x Microcontrollers SPRUH18I – JANUARY 2011 – REVISED JUNE 2022 Submit Document Feedback Copyright © 2022 Texas Instruments Incorporated...
Page 985 Unmask the channel that is mapped to XCEx. If the channel is also enabled by the corresponding receive channel enable bit, full transmission can occur. SPRUH18I – JANUARY 2011 – REVISED JUNE 2022 TMS320x2806x Microcontrollers Submit Document Feedback Copyright © 2022 Texas Instruments Incorporated...
Page 986 1h (R/W) = Receive frame synchronization is supplied by the sample rate generator. FSR is an output pin reflecting internal FSR, except when GSYNC = 1 in SRGR2 TMS320x2806x Microcontrollers SPRUH18I – JANUARY 2011 – REVISED JUNE 2022 Submit Document Feedback Copyright © 2022 Texas Instruments Incorporated...
Page 987 Internal MCLKR is driven by internal CLKX. The MCLKR pin is an output pin that reflects internal MCLKR. CLKX is derived according to the CLKXM bit. SPRUH18I – JANUARY 2011 – REVISED JUNE 2022 TMS320x2806x Microcontrollers Submit Document Feedback Copyright © 2022 Texas Instruments Incorporated...
Page 988 0h (R/W) = Receive data is sampled on the falling edge of MCLKR. 1h (R/W) = Receive data is sampled on the rising edge of MCLKR. TMS320x2806x Microcontrollers SPRUH18I – JANUARY 2011 – REVISED JUNE 2022 Submit Document Feedback Copyright © 2022 Texas Instruments Incorporated...
Page 989 0h (R/W) = Disable the channel that is mapped to RCEx. 1h (R/W) = Enable the channel that is mapped to RCEx. SPRUH18I – JANUARY 2011 – REVISED JUNE 2022 TMS320x2806x Microcontrollers Submit Document Feedback Copyright © 2022 Texas Instruments Incorporated...
Page 990 Unmask the channel that is mapped to XCEx. If the channel is also enabled by the corresponding receive channel enable bit, full transmission can occur. TMS320x2806x Microcontrollers SPRUH18I – JANUARY 2011 – REVISED JUNE 2022 Submit Document Feedback Copyright © 2022 Texas Instruments Incorporated...
Page 991 Unmask the channel that is mapped to XCEx. If the channel is also enabled by the corresponding receive channel enable bit, full transmission can occur. SPRUH18I – JANUARY 2011 – REVISED JUNE 2022 TMS320x2806x Microcontrollers Submit Document Feedback Copyright © 2022 Texas Instruments Incorporated...
Page 992 0h (R/W) = Disable the channel that is mapped to RCEx. 1h (R/W) = Enable the channel that is mapped to RCEx. TMS320x2806x Microcontrollers SPRUH18I – JANUARY 2011 – REVISED JUNE 2022 Submit Document Feedback Copyright © 2022 Texas Instruments Incorporated...
Page 993 Unmask the channel that is mapped to XCEx. If the channel is also enabled by the corresponding receive channel enable bit, full transmission can occur. SPRUH18I – JANUARY 2011 – REVISED JUNE 2022 TMS320x2806x Microcontrollers Submit Document Feedback Copyright © 2022 Texas Instruments Incorporated...
Page 994 Unmask the channel that is mapped to XCEx. If the channel is also enabled by the corresponding receive channel enable bit, full transmission can occur. TMS320x2806x Microcontrollers SPRUH18I – JANUARY 2011 – REVISED JUNE 2022 Submit Document Feedback Copyright © 2022 Texas Instruments Incorporated...
Page 995 0h (R/W) = Disable the channel that is mapped to RCEx. 1h (R/W) = Enable the channel that is mapped to RCEx. SPRUH18I – JANUARY 2011 – REVISED JUNE 2022 TMS320x2806x Microcontrollers Submit Document Feedback Copyright © 2022 Texas Instruments Incorporated...
Page 996 Unmask the channel that is mapped to XCEx. If the channel is also enabled by the corresponding receive channel enable bit, full transmission can occur. TMS320x2806x Microcontrollers SPRUH18I – JANUARY 2011 – REVISED JUNE 2022 Submit Document Feedback Copyright © 2022 Texas Instruments Incorporated...
Page 997 Unmask the channel that is mapped to XCEx. If the channel is also enabled by the corresponding receive channel enable bit, full transmission can occur. SPRUH18I – JANUARY 2011 – REVISED JUNE 2022 TMS320x2806x Microcontrollers Submit Document Feedback Copyright © 2022 Texas Instruments Incorporated...
Page 998 Reset type: SYSRSn 0h (R/W) = Receive interrupt on RRDY is disabled. 1h (R/W) = Receive interrupt on RRDY is enabled. TMS320x2806x Microcontrollers SPRUH18I – JANUARY 2011 – REVISED JUNE 2022 Submit Document Feedback Copyright © 2022 Texas Instruments Incorporated...
Page 999 16.6 Message Mailbox..............................1007 16.7 eCAN Configuration............................. 1010 16.8 Acceptance Filter..............................1023 16.9 eCAN Registers..............................1025 16.10 Message Data Registers (CANMDL, CANMDH)....................1053 SPRUH18I – JANUARY 2011 – REVISED JUNE 2022 TMS320x2806x Microcontrollers Submit Document Feedback Copyright © 2022 Texas Instruments Incorporated...
Page 1000 Using the CAN Bootloader at High Temperature Application Report Expert Materials • Calculator for CAN Bit Timing Parameters Application Report 1000 TMS320x2806x Microcontrollers SPRUH18I – JANUARY 2011 – REVISED JUNE 2022 Submit Document Feedback Copyright © 2022 Texas Instruments Incorporated...
Page 1001 The eCAN module is identical to the High-End CAN Controller (HECC) used in the TMS470 series of microcontrollers from Texas Instruments with some minor changes. The eCAN module features several enhancements (such as increased number of mailboxes with individual acceptance masks, time stamping, and so on) over the CAN module featured in the LF240xA series of devices.

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Texas Instruments TMS320 2806 Series Technical Reference Manual

Chapter 1 System Control and Interrupts

Chapter 2 Boot Rom

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Summary of Contents for Texas Instruments TMS320 2806 Series

Page 39: Table Of Contents

Page 40: Flash And Otp Memory Blocks

Page 52: Code Security Module (Csm)

Page 62: Clocking

Page 107: General-Purpose Input/Output (Gpio)

Page 157: Peripheral Frames

Page 167: Peripheral Interrupt Expansion (Pie)

Page 193: Vreg/Bor/Por

Page 196: Boot Rom Memory Map

Page 202: Bootloader Features

Page 236: Building The Boot Table

Page 240: Bootloader Code Overview

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Texas Instruments TMS320 2806 Series Technical Reference Manual

Chapter 1 System Control and Interrupts

Chapter 2 Boot Rom

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