Figure 14.11 Example Of Sci3 Transmission In Clocked Synchronous Mode - Renesas H8 Series Hardware Manual

Figure 14.12 shows a sample flow chart for serial data transmission. Even if the TDRE flag is
cleared to 0, transmission will not start while a receive error flag (OER, FER, or PER) is set to 1.
Make sure that the receive error flags are cleared to 0 before starting transmission.
Serial
clock
Serial
Bit 0
data
TDRE
TEND
LSI TXI interrupt
operation request
generated
User
processing

Figure 14.11 Example of SCI3 Transmission in Clocked Synchronous Mode

Bit 1 Bit 7
1 frame
TDRE flag TXI interrupt request generated
cleared
to 0
Data written
to TDR
Section 14 Serial Communication Interface 3 (SCI3)
Bit 0 Bit 1
1 frame
Rev. 3.00 Sep. 14, 2006 Page 221 of 408
Bit 6 Bit 7
TEI interrupt request
generated
REJ09B0105-0300