Register Descriptions; A/D Result Register (Adrr); A/D Mode Register (Amr) - Renesas F-ZTAT H8 Series Hardware Manual

12. A/D Converter
12.2

Register Descriptions

12.2.1

A/D Result Register (ADRR)

Bit
ADR7
Initial value
Undefined Undefined Undefined Undefined Undefined Undefined Undefined Undefined
Read/Write
The A/D result register (ADRR) is an 8-bit read-only register for holding the results of analog-to-
digital conversion.
ADRR can be read by the CPU at any time, but the ADRR values during A/D conversion are not
fixed.
After A/D conversion is complete, the conversion result is stored in ADRR as 8-bit data; this data
is held in ADRR until the next conversion operation starts.
ADRR is not cleared on reset.
12.2.2

A/D Mode Register (AMR)

Bit
CKS
Initial value
Read/Write R/W
AMR is an 8-bit read/write register for specifying the A/D conversion speed, external trigger
option, and the analog input pins.
Upon reset, AMR is initialized to H'30.
Bit 7—Clock Select (CKS): Bit 7 sets the A/D conversion speed.
Bit 7: CKS Conversion Period
0 62/φ (initial value)
1 31/φ
Operation is not guaranteed if the conversion time is less than 12.4 μs. Set bit 7 for a
Note: *
value of at least 12.4 μs.
Rev.3.00 Jul. 19, 2007 page 318 of 532
REJ09B0397-0300
7 6 5
ADR6 ADR5
R R R
7 6 5
⎯
TRGE
0 0 1
⎯
R/W
4 3
ADR4 ADR3 ADR2
R R
4 3
⎯
CH3
1 0
⎯
R/W
Conversion Time
φ = 2 MHz
31 μs
15.5 μs
2 1
ADR1 ADR0
R R
2 1
CH2 CH1 CH0
0 0
R/W R/W R/W
φ = 5 MHz
12.4 μs
⎯*
0
R
0
0