Programming The System Interface Unit; System Configuration And Protection Registers; Siu Module Configuration Register - Motorola MPC823e Reference Manual

System Interface Unit

12.12 PROGRAMMING THE SYSTEM INTERFACE UNIT

12.12.1 System Configuration and Protection Registers

12.12.1.1 SIU MODULE CONFIGURATION REGISTER. The SIU module configuration
register (SIUMCR) contains bits that configure various features in the system interface unit.
SIUMCR
BIT 0 1 2
FIELD
EARB EARP
RESET
0 0
R/W
R/W R/W
ADDR
BIT 16 17 18
FIELD
OPAR PNCS DPC
RESET
0 0 0
R/W
R/W R/W R/W
ADDR
EARB—External Arbitration
If the EARB bit is set, then external arbitration is assumed. If it is cleared, internal arbitration
is performed. For more information, see Section 13.4.6 Arbitration Phase-Related
Signals.
EARP—External Arbitration Request Priority
This field defines the priority of the external master's arbitration request. This field is valid
when EARB is cleared. 000 is the lowest priority level and 111 the highest. For more
information, refer to Figure 13-20 in Section 13 External Bus Interface.
Bits 4–7, 13, 24, and 28–31—Reserved
These bits are reserved and must be set to 0.
DSHW—Data Show Cycles
This bit selects the show cycle mode to be applied to data cycles. Instruction show cycles
are programmed in the ICTRL register. Refer to Section 20.6.2 Development Port
Registers for more information. This bit is locked by the DLK bit.
0 = Disable show cycles for all internal data cycles.
1 = Show address and data of all internal data cycles.
12-30
3 4 5 6 7
RESERVED
0
R/W
(IMMR & 0xFFFF0000) + 0x000
19 20 21 22 23
MPRE MLRC AEME SEME
0 0 0 0
R/W R/W R/W R/W
(IMMR & 0xFFFF0000)
MPC823e REFERENCE MANUAL
8 9 10 11 12
DSHW DBGC DBPC
0 0 0
R/W R/W R/W
24 25 26 27 28
RES GB5E B2DD B3DD
0 0 0 0
R/W R/W R/W R/W
+
0x002
13 14 15
RES FRC DLK
0 0 0
R/W R/W R/W
29 30 31
RESERVED
0
R/W
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