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Board Description and Memory Maps
1
System Configuration Register (SYSCR)
REG
BIT
FIELD
OPER
RESET
1-26
The states of the RD[0:31] DRAM data pins, which have weak internal
pull-ups, are latched by the upper Falcon chip at a rising edge of the power-
up reset and stored in this System Configuration Register to provide some
information about the system. Configuration is accomplished with external
pull-down resistors. This 32-bit read-only register is defined as follows:
System Configuration Register - $FEF80400
SYSID
SYSCLK
$FE
X
SYSID
System Identification. This field specifies the type of the
overall system configuration so that the software may
appropriately handle any software visible differences. For
the MVME3600 series and the MVME4600 series, this
field returns a value of $FE.
SYSCLK System Clock Speed. This field relays the system clock
speed and the PCI clock speed information as follows:
SYSCLK Value
0b0000 to 0b1100
0b1101
0b1110
0b1111
SYSXC
System External Cache Size. This field reflects size of the
look-aside cache on the system bus.
SYSXC
P0STAT
P1STAT
READ ONLY
X
X
System Clock Speed
Reserved
50 MHz
60 MHz
66.66 MHz
Computer Group Literature Center Web Site
X
$F
$F
PCI Clock Speed
Reserved
25 MHz
30 MHz
33.33 MHz
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