Cgm Programming Model; Pll Control Register; Table 4-2 Pll Control Register Description - Motorola MC68VZ328 User Manual

CGM Programming Model

4.4 CGM Programming Model
This section describes the two registers that enable and control the frequency of the CGM clocks.
4.4.1

PLL Control Register

The PLL control register (PLLCR) controls the frequency selection of the LCDCLK, SYSCLK, and
DMACLK. It also enables the output of the PLL and clock out/Port F pin 2 (CLKO/PF2). The settings for
each bit and field in the register are described in Table 4-2.
PLLCR
BIT
14 13
15
LCDCLK SEL
TYPE rw
0 0 1
RESET
Name
Reserved Reserved
Bits 15–14
LCDCLK SEL LCD Clock Select—This field controls the
Bits 13–11 divide ratio used by the LCD clock divider to
convert DMACLK to LCDCLK. This field can
be changed at any time.
SYSCLK SEL System Clock Select—This field controls the
Bits 10–8 divide ratio used by the SYSCLK divider to
convert DMACLK to SYSCLK. This field can
be changed at any time.
PRESC1 Prescaler 1 Select—This bit selects the divide
Bit 7 ratio of the prescaler 1.
Reserved Reserved
Bit 6
PRESC2 Prescaler 2 Select—This bit selects the divide
Bit 5 ratio used by the prescaler 2 to divide the out-
put of prescaler 1, producing DMACLK. This
field can be changed at any time.
CLKEN Clock Enable—This bit enables the buffered
Bit 4 output of the SYSCLK at the CLKO/PF2 pin
when bit 2 of the PFSEL register is also
cleared.
4-8
PLL Control Register
12 11 10 9 8
SYSCLK SEL
rw rw rw rw rw
0 0 1 0 0
Table 4-2. PLL Control Register Description
Description
MC68VZ328 User's Manual
7 6 5
PRESC1 PRESC2
rw rw
1 0 1
0x24B3
These bits are reserved and should be set to
0.
000 = DMACLK ÷ 2.
001 = DMACLK ÷ 4.
010 = DMACLK ÷ 8.
011 = DMACLK ÷ 16.
1xx = DMACLK ÷ 1 (%100 after reset).
000 = DMACLK ÷ 2.
001 = DMACLK ÷ 4.
010 = DMACLK ÷ 8.
011 = DMACLK ÷ 16.
1xx = DMACLK ÷ 1 (%100 after reset).
0 = PLLCLK ÷ 1.
1 = PLLCLK ÷ 2 (default).
This bit is reserved and should be set to 0.
0 = PR1CLK ÷ 1.
1 = PR1CLK ÷ 2 (default).
0 = CLKO enabled.
1 = CLKO disabled (default).
0xFFFFF200
4 3 2 1
CLKEN DISPLL WKSEL
rw rw rw
1 0 0 1
Setting
BIT
0
rw
1