Bus Arbitration Control - Motorola M68000 User Manual

UDS
High
Low
High
Low
Low
High
Low
*These conditions are a result of current implementation and may not appear
on future devices.
DS
Data Strobe ( ) (MC68008)
This three-state signal and R/W control the flow of data on the data bus of the
MC68008. Table 3-2 lists the combinations of these signals and the corresponding data
on the bus. When the R/W line is high, the processor reads from the data bus. When
the R/W line is low, the processor drives the data bus.
Data Transfer Acknowledge (
This input signal indicates the completion of the data transfer. When the processor
recognizes DTACK during a read cycle, data is latched, and the bus cycle is terminated.
When DTACK is recognized during a write cycle, the bus cycle is terminated.

3.4 BUS ARBITRATION CONTROL

The bus request, bus grant, and bus grant acknowledge signals form a bus arbitration
circuit to determine which device becomes the bus master device. In the 48-pin version of
the MC68008 and MC68EC000, no pin is available for the bus grant acknowledge signal;
this microprocessor uses a two-wire bus arbitration scheme. All M68000 processors can
use two-wire bus arbitration.
MOTOROLA M68000 8-/16-/32-BIT MICROPROCESSORS USER'S MANUAL
Freescale Semiconductor, Inc.
Table 3-1. Data Strobe Control of Data Bus
LDS W
R/
High —
Low High
Low High
High High
Low Low
Low Low
High Low
Table 3-2. Data Strobe Control
of Data Bus (MC68008)
DS W
R/
1 —
0 1 Valid Data Bits 7–0 (Read Cycle)
0 0 Valid Data Bits 7–0 (Write Cycle)
DTACK
).
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D8–D15 D0–D7
No Valid Data No Valid Data
Valid Data Bits Valid Data Bits
15–8 7–0
No Valid Data Valid Data Bits
7–0
Valid Data Bus No Valid Data
15–8
Valid Data Bits Valid Data Bits
15–8 7–0
Valid Data Bits Valid Data Bits
7–0* 7–0
Valid Data Bits Valid Data Bits
15–8 15–8*
D0–D7
No Valid Data
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