Bus Arbitration Control Signals; Bus Exception Control Signals - Motorola MC68020 User Manual

3.8 BUS ARBITRATION CONTROL SIGNALS

The following signals are the bus arbitration control signals used to determine which
device in a system is the bus master. Note that BGACK is implemented in the MC68020
and not implemented in the MC68EC020.
Bus Request (BR)
This input signal indicates that an external device needs to become the bus master. BR
is typically a "wire-ORed" input (but does not need to be constructed from open-collector
devices). Refer to Section 5 Bus Operation for more information on MC68020 bus
arbitration. Refer to Section 5 Bus Operation and Appendix A Interfacing an
MC68EC020 to a DMA Device That Supports a Three-Wire Bus Arbitration
Protocol for more information on MC68EC020 bus arbitration.
Bus Grant (BG)
This output signal indicates that the MC68020/EC020 will release ownership of the bus
when the current processor bus cycle completes. Refer to Section 5 Bus Operation for
more information on MC68020 bus arbitration. Refer to Section 5 Bus Operation and
Appendix A Interfacing an MC68EC020 to a DMA Device That Supports a Three-
Wire Bus Arbitration Protocol for more information on MC68EC020 bus arbitration.
Bus Grant Acknowledge (BGACK, MC68020 only)
This input signal indicates that an external device has become the bus master. Refer to
Section 5 Bus Operation for more information on MC68020 bus arbitration. Refer to
Section 5 Bus Operation and Appendix A Interfacing an MC68EC020 to a DMA
Device That Supports a Three-Wire Bus Arbitration Protocol for more information
on MC68EC020 bus arbitration.
BGACK is not implemented in the MC68EC020.

3.9 BUS EXCEPTION CONTROL SIGNALS

The following signals are the bus exception control signals for the MC68020/EC020.
Reset (RESET)
This bidirectional open-drain signal is used to initiate a system reset. An external reset
signal resets the MC68020/EC020 as well as all external devices. A reset signal from
the processor (asserted as part of the RESET instruction) resets external devices only;
the internal state of the processor is not altered. Refer to Section 5 Bus Operation for
a description of reset bus operation and Section 6 Exception Processing for
information about the reset exception.
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