Pci Bus Arbiter Operation - Motorola MPC8240 User Manual

PCI Bus Arbitration
Note that the latency timer parameter in the PCI latency timer register (PLTR) can affect
the streaming of data to the PCI bus. If the latency timer is set to be a shorter period than
the time required to transfer 4 Kbytes, then the PCI stream breaks when another PCI master
is granted mastership of the PCI bus. The latency timer parameter in the PCI latency timer
register (PLTR) is further described in Section 4.2.6, "Latency Timer—Offset 0x0D."
Thus, similar to processor-initiated transactions, DMA-initiated transactions to the PCI bus
may be interrupted before completion by the loss of mastership on the PCI bus or by the
PCI latency timer. This case does not constitute a PCI transaction boundary, and when the
MPC8240 regains mastership of the external PCI bus, the DMA stream in progress
continues without rearbitration with the processor.

7.2.2 PCI Bus Arbiter Operation

The following subsections describe the operation of the on-chip PCI arbiter that arbitrates
between external PCI masters and the internal PCI bus master of the MPC8240.
The on-chip PCI arbiter uses a programmable two-level, round-robin arbitration algorithm.
Each of the five external masters, plus the MPC8240, can be programmed for two priority
levels, high or low, using the appropriate bits in the PACR. Within each priority group (high
or low), the PCI bus grant is asserted to the next requesting device in numerical order, with
the MPC8240 positioned before device 0.
Conceptually, the lowest priority device is the master that is currently using the bus, and the
highest priority device is the device that follows the current master in numerical order and
group priority. This is considered to be a fair algorithm, since a single device cannot prevent
other devices from having access to the bus; it automatically becomes the lowest priority
device as soon as it begins to use the bus. If a master is not requesting the bus, then its
transaction slot is given to the next requesting device within its priority group.
A grant is awarded to the highest priority requesting device as soon as the current master
begins a transaction; however, the granted device must wait until the bus is relinquished by
the current master before initiating a transaction.
The grant given to a particular device may be removed and awarded to another, higher
priority device, whenever the higher priority device asserts its request. If the bus is idle
when a device requests the bus, then for one clock cycle the arbiter withholds the grant. The
arbiter re-evaluates the priorities of all requesting devices and grants the bus to the highest
priority device in the following clock cycle. This allows a turnaround clock when a higher
priority device is using address stepping or when the bus is parked.
The low-priority group collectively has one bus transaction request slot in the high-priority
group. Mathematically, if there are N high-priority devices, and M low-priority devices,
then each high-priority device is guaranteed to get at least 1 of N+1 bus transactions, and
each low priority device is guaranteed to get at least 1 of (N+1) x M bus transactions, with
one of the low-priority devices receiving the grant in 1 of N+1 bus transactions. If all
7-6 MPC8240 Integrated Processor User's Manual