Interrupt Control Signals; Interrupt Priority Level Signals; Interrupt Pending (Lpend); Autovector (Avec) - Motorola MC68030 User Manual

5.8 INTERRUPT CONTROL SIGNALS
The following signals are the interrupt control signals for the MC68030.
5.8.1 Interrupt Priority Level Signals
These input signals provide an indication of an interrupt condition and the
encoding of the interrupt level from a peripheral or external prioritizing cir-
cuitry. IPL2 is the most significant bit of the level number. For example, since
the IPLn signals are active low, IPLO-IPL2 equal to $5 corresponds to an
interrupt request at interrupt level 2. Refer to 8.1.9 Interrupt Exceptions for
information on MC68030 interrupts.
5.8.2 Interrupt Pending (lPEND)
This output signal indicates that an interrupt request has been recognized
internally and exceeds the current interrupt priority mask in the status register
(SR). This output is for use by external devices (coprocessors and other bus
masters, for example) to predict processor operation on the following in-
struction boundaries. Refer to 8.1.9 Interrupt Exceptions for interrupt infor-
mation. Also, refer to 7.4.1 Interrupt Acknowledge Bus Cycles for bus
information related to interrupts.
5.8.3 Autovector (AVEC)
This input signal indicates that the MC68030 should generate an automatic
vector during an interrupt acknowledge cycle. Referto 7.4.1.2 AUTOVECTOR
INTERRUPT ACKNOWLEDGE CYCLE for more information about automatic
vectors.
5.9 BUS ARBITRATION CONTROL SIGNALS
The following signals are the three bus arbitration control signals used to
determine which device in a system is the bus master.
5.9.1 Bus Request (BR)
5-8
This input signal indicates that an external device needs to become the bus
master. This is typically a "wire-ORed" input (but does not need to be con-
structed from open-collector devices). Refer to 7.7 BUS ARBITRATION for
more information.
MC68030 USER'S MANUAL
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