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Table 13-1. Bus Interface Signals (Continued)
MNEMONIC
PINS
ARBITRATION
BR
BG
BB
NOTE:
O indicates an output from the MPC823e and I indicates an input.
13.4 BUS INTERFACE OPERATION
The MPC823e generates a system clock output (CLKOUT) that sets the frequency of
operation for the bus interface. Internally, the MPC823e uses a phase-lock loop (PLL) circuit
to generate a master clock for all of the core circuitry, which is phase-locked to the CLKOUT
output signal.
All signals for the MPC823e bus interface are specified with respect to the rising-edge of the
external CLKOUT and are guaranteed to be sampled as inputs or changed as outputs with
respect to that edge. Since the same clock edge is referenced for driving or sampling the
bus signals, the possibility of clock skew could exist between various modules in a system
because of routing or using multiple clock lines. It is your responsibility to handle any clock
skew problems that could occur as a result of layout, lead-length, and physical routing.
MOTOROLA
ACTIVE
I/O
1
Low
I
Bus Request —When the internal arbiter is asserted,
it indicates that an external master is requesting the
bus.
O
Driven by the MPC823e when the internal arbiter is
disabled and the chip is not parked .
1
Low
O
Bus Grant —When the internal arbiter is enabled, the
MPC823e asserts this signal to indicate that an
external master can assume ownership of the bus and
begin a bus transaction. The BG signal must be
qualified by the master requesting the bus to ensure it
is the bus owner:
Qualified BG = BG & BB
I
When the internal arbiter is disabled, the BG is
sampled and properly qualified by the MPC823e
when an external bus transaction is to be executed by
the chip.
1
Low
O
Bus Busy —When the internal arbiter is enabled, the
MPC823e asserts this signal to indicate that it is the
current owner of the bus. When the internal arbiter is
disabled, it will assert this signal after the external
arbiter grants the chip ownership of the bus and it is
ready to start the transaction.
I
When the internal arbiter is enabled, the MPC823e
samples this signal to get an indication of when the
external master ended its bus tenure (BB negated).
When the internal arbiter is disabled, the BB is
sampled to properly qualify the BG line when an
external bus transaction is to be executed by the chip.
MPC823e REFERENCE MANUAL
External Bus Interface
DESCRIPTION
13-7
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