Configuration/Status Register (Csr) - Motorola DigitalDNA ColdFire MCF5272 User Manual

Programming Model
31
Field BSTAT
Reset 0000
1
R/W R
15 14 13
Field MAP TRC EMU
Reset 0 0
R/W R/W R/W R/W
DRc[4–0]
1
Bit 7 is reserved for Motorola use and must be written as a zero.
Figure 5-7. Configuration/Status Register (CSR)
Table 5-8 describes CSR fields.
Bit Name
31–28 BSTAT Breakpoint status. Provides read-only status information concerning hardware breakpoints. BSTAT
is cleared by a TDR write or by a CSR read when either a level-2 breakpoint is triggered or a
level-1 breakpoint is triggered and the level-2 breakpoint is disabled.
0000 No breakpoints enabled
0001 Waiting for level-1 breakpoint
0010 Level-1 breakpoint triggered
0101 Waiting for level-2 breakpoint
0110 Level-2 breakpoint triggered
27 FOF Fault-on-fault. If FOF is set, a catastrophic halt occurred and forced entry into BDM. FOF is cleared
whenever CSR is read.
26 TRG Hardware breakpoint trigger. If TRG is set, a hardware breakpoint halted the processor core and
forced entry into BDM. Reset, the debug
25 HALT Processor halt. If HALT is set, the processor executed a HALT and forced entry into BDM. Reset,
the debug
24 BKPT Breakpoint assert. If BKPT is set, BKPT was asserted, forcing the processor into BDM. Reset, the
debug
GO
23–20 HRL Hardware revision level. Indicates the level of debug module functionality. An emulator could use
this information to identify the level of functionality supported.
0000 Initial debug functionality (Revision A) (this is the only valid value for the MCF5272)
19–17 — Reserved, should be cleared.
16 IPW Inhibit processor writes. Setting IPW inhibits processor-initiated writes to the debug module's
programming model registers. IPW can be modified only by commands from the external
development system.
15 MAP Force processor references in emulator mode.
0 All emulator-mode references are mapped into supervisor code and data spaces.
1 The processor maps all references while in emulator mode to a special address space, TT = 10,
TM = 101 or 110.
14 TRC Force emulation mode on trace exception. If TRC = 1, the processor enters emulator mode when a
trace exception occurs. If TRC=0, the processor enters supervisor mode.
5-10
28 27 26
FOF TRG HALT BKPT
0 0
R R
12 11 10
DDC UHE
0 00 0
R/W R/W
Table 5-8. CSR Field Descriptions
command, or reading CSR clear HALT.
GO
command, or reading CSR clear BKPT.
MCF5272 User's Manual
25 24 23
HRL
0 0 0000
R R R
9 8 7 6
1
BTB — NPL
00 0 0
R/W R R/W R/W R/W
0x00
Description
command, or reading CSR clear TRG.
GO
20 19
—
0 0
—
5 4 3
IPI SSM —
0 0 0000
—
17 16
IPW
0 0
R/W
0