Pci Status Register-Offset 0X06 - Motorola MPC8240 User Manual

PCI Interface Configuration Registers
The 2-byte PCI status register, shown in Figure 4-4, is used to record status information for
PCI bus-related events. The definition of each bit is given in Table 4-6. Only 2-byte
accesses to address offset 0x06 are allowed.
Table 4-5. Bit Settings for PCI Command Register—0x04
Bits Name
15–10 —
9 Fast back-to-back
8 SERR
7 —
6 Parity error response
5 —
4 Memory-write-and-
invalidate
3 Special cycles
2 Bus master
1 Memory space
0 I/O space
4.2.2 PCI Status Register—Offset 0x06
The 2-byte PCI status register, shown in Figure 4-4, is used to record status information for
PCI bus-related events. The definition of each bit is given in Table 4-6. Only 2-byte
accesses to address offset 0x06 are allowed.
4-12
Reset
Value
All 0s These bits are reserved.
0 This bit is hardwired to 0, indicating that the MPC8240 does not run fast
back-to-back transactions.
0 This bit controls the SERR driver of the MPC8240. This bit (and bit 6)
must be set to report address parity errors.
0 Disables the SERR driver
1 Enables the SERR driver
0 This bit is reserved.
0 This bit controls whether the MPC8240 responds to parity errors.
0 Parity errors are ignored and normal operation continues.
1 Action is taken on a parity error. See Chapter 13, "Error Handling," for
more information.
0 This bit is reserved.
0 This bit enables generation of the memory-write-and-invalidate command
by the MPC8240 as a master.
0 Memory-write command used by MPC8240.
1 Memory-write-and-invalidate command used by MPC8240.
0 This bit is hardwired to 0, indicating that the MPC8240 (as a target)
ignores all special-cycle commands.
1 (host) This bit controls whether the MPC8240 can act as a master on the PCI
0 (agent) bus. Note that if this bit is cleared, processor-to-PCI writes cause the data
to be held until it is enabled. Processor to PCI reads with master disabled
cause a machine check exception (if enabled).
0 Disables the ability to generate PCI accesses
1 Enables the MPC8240 to behave as a PCI bus master
0 This bit controls whether the MPC8240 (as a target) responds to memory
accesses.
0 The MPC8240 does not respond to PCI memory space accesses.
1 The MPC8240 responds to PCI memory space accesses.
0 This bit is hardwired to 0, indicating that the MPC8240 (as a target) does
not respond to PCI I/O space accesses.
MPC8240 Integrated Processor User's Manual
Description