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Memory Management Unit
11.5 TRANSLATION TABLE STRUCTURE
The MPC823e memory management unit includes special hardware to assist in a two-level
software tablewalk. Other table structures are not precluded. Figure 11-2 and Figure 11-3
illustrate the two levels of translation table structures supported by MPC823e special
hardware. When MD_CTR
= 1, the tablewalk begins at the level one base address in
TWAM
the M_TWB register. The level one table is indexed by the ten most-significant bits of the
effective address to get the level one page descriptor. For 8M pages, there must be two
identical entries in the level one table for either Bit 9 =0 or Bit 9 =1. See Table 11-2 for more
information. The level two base address from the level one descriptor is indexed by the next
ten least-significant bits to find the level two page descriptor. For pages larger than 4K, the
entry in the level two table must be duplicated according to the page size. See Table 11-3
for more information.
During address translation by the memory management unit, the most-significant bits of the
missed effective address are replaced by the real page address bits from the level two page
descriptor. The number of replaced bits depends on the page size. The rest of the real
address bits are taken directly from the effective address. When MD_CTR
= 0, the
TWAM
tablewalk begins at the level one base address placed in the M_TWB register. The level one
table is indexed by the 12 most-significant bits of the effective address to get the level one
page descriptor. For 8M pages, there must be eight identical entries in the level one table
for bits 9-11 of the effective address. The level two base address from the level one
descriptor is indexed by the next ten least-significant bits to find the level two page
descriptor. For pages larger than 1K, the entry in the level two table must be duplicated
according to the page size.
MOTOROLA
MPC823e REFERENCE MANUAL
11-5
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