Address Bus (A[22:0]/Sdram_Adr[13:0]) - Motorola DigitalDNA ColdFire MCF5272 User Manual

Address Bus (A[22:0]/SDRAM_ADR[13:0])

Table 19-2. Signal Name and Description by Pin Number (Continued)
Map
BGA
0 (Reset)
Pin
P1 PA7
P2 High Z
P3 INT2
P4 QSPI_Din
P5 High Z
P6 E_COL
P7 E_RxD0
P8 E_TxEN
P9 PB11
P10 PB15
P11 CS2
P12 CS6
P13 OE/RD
P14 R/W
19.2 Address Bus (A[22:0]/SDRAM_ADR[13:0])
The 23 dedicated address signals, A[22:0], define the address of external byte, word, and
longword accesses. These three-state outputs are the 23 lsbs of the internal 32-bit address
bus and are multiplexed with the SDRAM controller row and column addresses
(SDRAM_ADR[13:0]).
Fourteen address signals are used for connecting to SDRAM devices as large as 256 Mbits.
The MCF5272 supports SDRAM widths of 16 or 32 bits. For a 32-bit width, SDRAM
address signals are multiplexed starting with A2. For a 16-bit width, address signals are
multiplexed starting with A1.
19.3 Data Bus (D[31:0])
The 32-bit, three-state, bidirectional, non-multiplexed data bus transfers data to and from
the MCF5272. A read or write operation can transfer 8, 16, or 32 bits in one bus cycle.
19-16
Pin Functions
1 2
QSPI_CS3 DOUT3
– DIN3
– –
– –
PWM_ TOUT1
OUT1
– –
– –
– –
E_RxD3 –
E_MDC –
– –
– –
– –
– –
MCF5272 User's Manual
Name
3
– PA7/QSPI_CS3/DOUT3
INT4 DIN3/INT4
– INT2
– QSPI_Din
– PWM_OUT1/TOUT1
– E_COL
– E_RxD0
– E_TxEN
– PB11/E_RxD3
– PB15/E_MDC
– CS2
– CS6/AEN
– OE/RD
– R/W
Description
PA7/QSPI chip select
4/PLIC port 3 data
output
Interrupt 4 input/PLIC
port 3 data input
Interrupt input 1
QSPI data input
PWM output compare 1
/Timer 1 output
compare
Collision
Ethernet Rx data
Ethernet Tx enable
Port B bit 11/Rx data bit
3 (100 Base-T Ethernet
only)
Port B bit 15/
Management Channel
Clock (100 Base-T only)
Chip select 2
Chip select 6
Output enable/Read
Read/Write
I/O
I/O
I
I
I
O
I
I
O
I/O
I/O
O
O
O
O