Lacd (M) Rate Control Register (Acdrc); Line Buffer Control Registers; Pixel Clock Divider Register (Pxcd); Clocking Control Register (Ckcon) - Motorola DragonBall MC68328 User Manual

4.7.4.3 LACD (M) RATE CONTROL REGISTER (ACDRC).

ACD3-ACD0
ACD toggle-rate control code. The ACD signal will toggle once every 1 to 16 FLM cycles
based on the value specified in ACDRC register. The actual number of FLM cycles is the
value programmed plus one. Shorter cycles tend to give better results.

4.7.5 Line Buffer Control Registers

4.7.5.1 PIXEL CLOCK DIVIDER REGISTER (PXCD).

PCD5-PCD0
The PIX clock from the PLL is divided by N (PCD5-0 plus one) to yield the actual pixel
clock. Values of 1-63 will yield N=2 to 64. If set to 0 (N=1), the PIX clock will be used di-
rectly, bypassing the divider circuit. Input source is selected by PCDS in CKCON register.

4.7.5.2 CLOCKING CONTROL REGISTER (CKCON).

LCDCON
This bit controls the LCDC block.
0 = Disable LCDC
1 = Enable LCDC
The internal LCDC logic will be switched off in step with the FLM
pulse.
DMA16
This bit controls the length of the DMA burst.
0 = 8 words burst length
1 = 16 words burst length
MOTOROLA MC68328 DRAGONBALL PROCESSOR USER'S MANUAL
7 6 5
UNUSED
Address: $(FF)FFFA23
Figure 4-18. LACD Rate Control Register
Alternate Crystal Direction Control
7 6 5
UNUSED PCD5
Address: $(FF)FFFA25
Figure 4-19. Pixel Clock Divider Register
Pixel Clock Divider
7 6 5
LCDON DMA16 WS1
Address: $(FF)FFFA27
Figure 4-20. Clocking Control Register
4 3 2 1
ACD3 ACD2 ACD1
Reset Value: $00
4 3 2 1
PCD4 PCD3 PCD2 PCD1
Reset Value: $00
4 3 2 1
WS0 UNUSED DWIDTH PCDS
Reset Value: $00
NOTE
LCD Controller
0
ACD0
0
PCD0
0
4-17