The Low-Power Clock Divider - Motorola MPC823e Reference Manual

Clocks and Power Control
The phase jitter is a variation in the skew that occurs between the falling edges of the EXTAL
and CLKOUT pins for a specific temperature, voltage, input frequency, MF, and capacitive
load on the CLKOUT pin. These variations are a result of the PLL locking mechanism. For
input frequencies greater than 15MHz and MF ≤ 2, this jitter is less than ± 0.6ns. Otherwise,
this jitter is not guaranteed. However, for MF<10 and input frequencies greater than 10MHz,
this jitter is less than ± 2ns.
The frequency jitter is defined as the frequency variation of the CLKOUT pin. For small
multiplication factors (MF<10), this jitter is smaller than 0.5%. For mid-range multiplication
factors (10<MF<500), this jitter is between 0.5% and -2%. For large multiplication factors
(MF>500), the frequency jitter is 2–3%. The maximum input frequency jitter on the EXTAL
pin is 0.5%. If the rate of change of the frequency at the EXTAL pin is slow (it does not jump
between the minimum and maximum values in one cycle), the maximum jitter can be 2%.

5.3.3 The Low-Power Clock Divider

The output of the SPLL is sent to a low-power divider that generates other clocks for normal
operation, but also has the ability to divide the output frequency of the VCO before it
generates the SYNCCLK, LCDCLK, LCDCLK50, BRGCLK, and GCLKx (which is sent to the
rest of the MPC823e). GCLKxC is the system timing reference for the core, instruction and
data caches, and memory management unit. GCLKx is the system timing reference for the
other modules. GCLKx_50 operates at a frequency that is half the GCLKx frequency. The
frequency ratio between GCLKx and GCLKx_50 is determined by the EBDF bit in the SCCR.
5-14 MPC823e REFERENCE MANUAL MOTOROLA