Interrupt Control Register 2 (Icr2) - Motorola DigitalDNA ColdFire MCF5272 User Manual

Bits Name
31, 27, PI Pending interrupt. Writing a 1 enables the value for the corresponding IPL field to be set. Note:
23, 19, for external interrupts only, writing a one to this bit clears the corresponding interrupt latch.
15, 11, The external interrupt must be toggled before another interrupt is latched. For all on-chip
7, 3 interrupt sources, this bit is cleared when the interrupt is cleared in the module registers.
0 No interrupt pending
1 An interrupt is pending.
30–28, IPL Interrupt priority level. Specifies the IPL for the corresponding interrupt source. This field can
26–24, be changed only when a 1 is simultaneously written to the corresponding PI bit.
22–20, 000 The corresponding INT source is inhibited and cannot generate interrupts. The state of
18–16,
001–111The corresponding INT source is enabled and generates an interrupt with the
14-12,
indicated priority level.
10–8,
6–4, 2–0

7.2.2.2 Interrupt Control Register 2 (ICR2)

ICR2, Figure 7-3, is used to configure interrupts from various on-chip sources.
31 30
Field UART1PI UART11IPL
Reset
15 14
Field USB0PI USB0IPL
Reset
R/W
Addr
Table 7-3 describes ICR2 fields.
7.2.2.3 Interrupt Control Register 3 (ICR3)
ICR3, Figure 7-4, is used to configure interrupts from various on-chip sources.
Table 7-3. ICR Field Descriptions
the signal can still be read in the ISR.
28 27 26
UART2PI UART2IPL
0000_0000_0000_0000
12 11 10
USB1PI USB1IPL
0000_0000_0000_0000
Figure 7-3. Interrupt Control Register 2 (ICR2)
Chapter 7. Interrupt Controller
Description
24 23 22
PLIPPI PLIPIPL
8 7 6
USB2PI USB2IPL
R/W
MBAR + 0x024
Interrupt Controller Registers
20 19 18
PLIAPI PLIAIPL
4 3 2
USB3PI USB3IPL
16
0
7-5