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12.3.3 Programming the Interrupt Controller
The system interface unit's interrupt controller consists of the SIPEND, SIMASK, SIEL and
SIVEC registers.
12.3.3.1 SIU INTERRUPT PENDING REGISTER. The 32-bit SIU interrupt pending
(SIPEND) register contains bits that individually correspond to an interrupt request. If they
are set, the bits associated with internal exceptions indicate that an interrupt service is
requested, if they are not masked by the corresponding bit in the SIMASK register. These
bits reflect the status of the internal requesting device and they are cleared when the
appropriate actions are software-initiated in the device itself. The bits associated with the
IRQx pins have a different behavior depending on the sensitivity defined for them in the SIEL
register. When an IRQx signal is defined as a "level" interrupt the corresponding bit behaves
similar to the bits associated with internal interrupt sources. When an IRQx signal is defined
as an "edge" interrupt and if the corresponding bit is set, it indicates that a falling edge was
detected on the line. These bits are reset by writing a 1 to them.
SIPEND
BIT
0
1
2
FIELD
IRQ0 LVL0 IRQ1 LVL1 IRQ2 LVL2 IRQ3 LVL3 IRQ4 LVL4 IRQ5 LVL5 IRQ6 LVL6 IRQ7
RESET
0
0
0
R/W
R/W
R/W
R/W
ADDR
BIT
16
17
18
FIELD
RESET
R/W
ADDR
IRQ—Interrupt Request 0–7
When set, this field indicates a pending external IRQx interrupt of a corresponding value.
See Figure 12-2 for more information.
0 = The appropriate interrupt is not pending.
1 = The appropriate interrupt is pending.
LVL—Level 0–7
When set, this field indicates a pending internal level interrupt of a corresponding value. See
Figure 12-2 for more information.
0 = The appropriate interrupt is not pending.
1 = The appropriate interrupt is pending.
MOTOROLA
3
4
5
6
7
0
0
0
0
0
R/W
R/W
R/W
R/W
R/W
(IMMR & 0xFFFF0000) + 0x010
19
20
21
22
23
RESERVED
0
R/W
(IMMR & 0xFFFF0000) + 0x012
MPC823e REFERENCE MANUAL
System Interface Unit
8
9
10
11
12
0
0
0
0
0
R/W
R/W
R/W
R/W
R/W
24
25
26
27
28
13
14
15
LV7
0
0
0
R/W
R/W
R/W
29
30
31
12-7
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