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M16C/5L Group, M16C/56 Group
23.1.10.1 RFE Bit
When the RFE bit is set to 1, the receive FIFO is enabled.
When this bit is set to 0, the receive FIFO is disabled for reception and becomes empty (RFEST bit =
1).
Do not set this bit to 1 in normal mailbox mode (MBM bit in the C0CTLR register = 0).
Due to hardware protection, the RFE bit is not set to 0 by writing 0 by a program during the following
period:
Hardware protection is started
• From the acceptance filter procedure (the beginning of the CRC field)
Hardware protection is released
• If the receive FIFO is specified to receive the incoming message, after the received data is stored
into the receive FIFO or a CAN bus error occurs. (i.e. a maximum period of hardware protection is
from the beginning of the CRC field to the end of the seventh bit of EOF.)
• If the receive FIFO is not specified to receive the message, after the acceptance filter procedure.
23.1.10.2 RFUST Bit
The RFUST bit indicates the number of unread messages in the receive FIFO.
The value of this bit is initialized to 000b when the RFE bit is set to 0.
23.1.10.3 RFMLF Bit
The RFMLF bit is set to 1 (receive FIFO message lost has occurred) when the receive FIFO receives a
new message and the receive FIFO is full. The timing for setting this bit to 1 is at the end of the sixth bit
of EOF.
The RFMLF bit is set to 0 by writing 0 by a program.
In both overwrite and overrun modes, this bit cannot be set to 0 (receive FIFO message lost has not
occurred) by writing 0 by a program due to hardware protection during the five cycles of fCAN following
the sixth bit of EOF, if the receive FIFO is full and determined to receive the message.
23.1.10.4 RFFST Bit
The RFFST bit is set to 1 (receive FIFO is full) when the number of unread messages in the receive
FIFO is 4. This bit is set to 0 (receive FIFO is not full) when the number of unread messages in the
receive FIFO is less than 4. This bit is set to 0 when the RFE bit is 0.
23.1.10.5 RFWST Bit
The RFWST bit is set to 1 (receive FIFO is buffer warning) when the number of unread messages in the
receive FIFO is 3. This bit is set to 0 (receive FIFO is not buffer warning) when the number of unread
messages in the receive FIFO is less than 3 or equal to 4. This bit is set to 0 when the RFE bit is 0.
23.1.10.6 RFEST Bit
The RFEST bit is 1 (no unread message in receive FIFO) when the number of unread messages in the
receive FIFO is 0. This bit is set to 1 when the RFE bit is set to 0. The RFEST bit is set to 0 (unread
message in receive FIFO) when the number of unread messages in the receive FIFO is one or more.
Figure 23.12 shows the receive FIFO mailbox operation.
R01UH0127EJ0110 Rev.1.10
Sep 01, 2011
23. CAN Module
Page 571 of 803
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