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M16C/5L Group, M16C/56 Group
22.2.1
I2C0 Data Shift Register (S00)
I2C0 Data Shift Register
b7
2
When the I
C interface is a transmitter, write transmit data to the S00 register. When the I
a receiver, received data can be read from the S00 register. In master mode, this register is also used to
generate a start condition or stop condition on a bus. (Refer to 22.3.2 "Generating a Start Condition"
and 22.3.3 "Generating a Stop Condition".)
Write to the S00 register when the ES0 bit in the S1D0 register is 1 (I
Do not write to the S00 register when transmitting/receiving data.
2
When the I
C interface is a transmitter, the data in the S00 register is transmitted to other devices. The
MSB (bit 7) is transmitted first, synchronizing with the SCLMM clock. Every time 1-bit data is output, the
S00 register value is shifted 1 bit to the left.
2
When the I
C interface is a receiver, data is transferred to the S00 register from other devices. The LSB
(bit 0) is input first, synchronizing with the SCLMM clock. Every time 1-bit data is output, the S00
register value is shifted 1 bit to the left. Figure 22.2 shows Timing to Store Received Data to the S00
Register.
SCLMM
SDAMM
Internal SCL
Internal SDA
Shift clock
(internal signal)
S00 register
tdfil: Noise filter delay time, one to two fVIIC cycles
tdsft: Shift clock delay time, one fVIIC cycle
Figure 22.2
Timing to Store Received Data to the S00 Register
R01UH0127EJ0110 Rev.1.10
Sep 01, 2011
b0
Symbol
S00
Transmit/receive data is stored.
tdfil
Address
02B0h
Function
2
tdfil
tdsft
Data is stored to bit 0 at the rising edge of shift clock.
Data
Register value is shifted 1 bit to the left.
2
22. Multi-master I
C-bus Interface
Reset Value
XXh
RW
RW
2
C interface is
C interface enabled).
Data
Page 503 of 803
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