Page 1 All information contained in these materials, including products and product specifications, represents information on the product at the time of publication and is subject to change by Renesas Technology Corp. without notice. Please review the latest information published by Renesas Technology Corp. through various means, including the Renesas Technology Corp.
Page 2 Please be sure to implement safety measures to guard against the possibility of physical injury, and injury or damage caused by fire in the event of the failure of a Renesas product, such as safety design for hardware and software including but not limited to redundancy, fire control and malfunction prevention, appropriate treatment for aging degradation or any other applicable measures.
Page 3 General Precautions in the Handling of MPU/MCU Products The following usage notes are applicable to all MPU/MCU products from Renesas. For detailed usage notes on the products covered by this manual, refer to the relevant sections of the manual. If the descriptions under General Precautions in the Handling of MPU/MCU Products and in the body of the manual differ from each other, the description in the body of the manual takes precedence.
Page 4: How To Use This Manual
The following documents apply to the M16C/28 Group (M16C/28 and M16C/28B). Make sure to refer to the latest versions of these documents. The newest versions of the documents listed may be obtained from the Renesas Technology Web site.
Page 5 Notation of Numbers and Symbols The notation conventions for register names, bit names, numbers, and symbols used in this manual are described below. Register Names, Bit Names, and Pin Names Registers, bits, and pins are referred to in the text by symbols. The symbol is accompanied by the word “register,”...
Page 6 Register Notation The symbols and terms used in register diagrams are described below. XXX Register Symbol Address After Reset Bit Symbol Bit Name Function b1 b0 XXX bits XXX0 1 0: XXX 0 1: XXX 1 0: Do not set. XXX1 1 1: XXX Nothing is assigned.
Page 7 List of Abbreviations and Acronyms Abbreviation Full Form ACIA Asynchronous Communication Interface Adapter bits per second Cyclic Redundancy Check Direct Memory Access DMAC Direct Memory Access Controller Global System for Mobile Communications Hi-Z High Impedance IEBus Inter Equipment bus Input/Output IrDA Infrared Data Association Least Significant Bit...
Page 8: Table Of Contents
Table of Contents Quick Reference by Address ................B-1 1. Overview ......................1 1.1 Features ........................... 1 1.1.1 Applications ........................ 1 1.1.2 Specifications ......................2 1.2 Block Diagram ........................4 1.3 Product Information ......................6 1.4 Pin Assignment ....................... 10 1.5 Pin Description .......................
Page 9 5. Reset ......................32 5.1 Hardware Reset ......................32 5.1.1 Hardware Reset 1 ....................32 5.1.2 Hardware Reset 2 ....................32 5.2 Software Reset ....................... 33 5.3 Watchdog Timer Reset ....................33 5.4 Oscillation Stop Detection Reset ..................33 5.5 Voltage Detection Circuit ....................35 5.5.1 Low Voltage Detection Interrupt ................
Page 10 9.2 Interrupts and Interrupt Vector ..................70 9.2.1 Fixed Vector Tables ....................70 9.2.2 Relocatable Vector Tables ..................71 9.3 Interrupt Control ......................72 9.3.1 I Flag ........................75 9.3.2 IR Bit ........................75 9.3.3 ILVL2 to ILVL0 Bits and IPL..................75 9.4 Interrupt Sequence ......................
Page 11 12.2 Timer B ........................114 12.2.1 Timer Mode ......................116 12.2.2 Event Counter Mode .................... 117 12.2.3 Pulse Period and Pulse Width Measurement Mode ..........118 12.2.4 A/D Trigger Mode ....................120 12.3 Three-phase Motor Control Timer Function ..............122 12.3.1 Position-Data-Retain Function ................
Page 12 15.1.3 Single Sweep Mode .................... 227 15.1.4 Repeat Sweep Mode 0 ..................229 15.1.5 Repeat Sweep Mode 1 ..................231 15.1.6 Simultaneous Sample Sweep Mode ..............233 15.1.7 Delayed Trigger Mode 0 ..................236 15.1.8 Delayed Trigger Mode 1 ..................242 15.2 Resolution Select Function ..................
Page 13 16.6.4 Bits 4,5 : SDA/SCL Logic Output Value Monitor Bits SDAM/SCLM ....269 16.6.5 Bits 6,7 : I C System Clock Select Bits ICK0, ICK1 ..........269 16.6.6 Address Receive in STOP/WAIT Mode ............... 269 16.7 I C0 Control Register 2 (S4D0 Register) ..............270 16.7.1 Bit0: Time-Out Detection Function Enable Bit (TOE) ..........
Page 14 18.4 CPU Rewrite Mode ..................... 304 18.4.1 EW Mode 0 ......................305 18.4.2 EW Mode 1 ......................305 18.5 Register Description ....................306 18.5.1 Flash Memory Control Register 0 (FMR0) ............306 18.5.2 Flash Memory Control Register 1 (FMR1) ............307 18.5.3 Flash Memory Control Register 4 (FMR4) ............
Page 15 20. Precautions ....................350 20.1 SFR ..........................350 20.1.1 For 80-Pin and 85-Pin Package ................350 20.1.2 For 64-Pin Package ..................... 350 22.1.3 Register Setting ....................350 20.1.4 For Flash Memory (128K+4K) Version and Mask ROM Version ......351 20.2 Clock Generation Circuit ..................... 352 20.2.1 PLL Frequency Synthesizer .................
Page 16 20.11 Programmable I/O Ports ................... 372 20.12 Electric Characteristic Differences Between Mask ROM and Flash Memory Version ... 373 20.13 Mask ROM Version ....................374 20.13.1 Internal ROM Area ..................... 374 20.13.2 Reserved Bit ....................... 374 20.14 Flash Memory Version ....................375 20.14.1 Functions to Inhibit Rewriting Flash Memory Rewrite ........
Page 17 Quick Reference by Address Register Symbol Page Register Symbol Page Address Address 0000 0040 0001 0041 0002 0042 0003 0043 Processor mode register 0 INT3 interrupt control register INT3IC 0004 0044 IC/OC 0 interrupt control register ICOC0IC Processor mode register 1 0005 0045 System clock control register 0...
Page 18 Quick Reference by Address Register Symbol Page Register Symbol Page Address Address 0300 TM, WG register 0 141,142 G1TM0, G1PO0 0301 0302 TM, WG register 1 141,142 G1TM1, G1PO1 01B0 0303 01B1 0304 TM, WG register 2 141,142 G1TM2, G1PO2 01B2 0305 Flash memory control register 4...
Page 19 Quick Reference by Address Register Symbol Page Register Symbol Page Address Address Count start flag TABSR 101,115 0380 0340 Clock prescaler reset flag CPSRF 102,115 0381 0341 One-shot start flag ONSF 0382 0342 Timer A1-1 register TA11 Trigger select register TRGSR 102,129 0383...
Page 20 Quick Reference by Address Register Symbol Page Address 03C0 A/D register 0 03C1 03C2 A/D register 1 03C3 03C4 A/D register 2 03C5 03C6 A/D register 3 03C7 03C8 A/D register 4 03C9 03CA A/D register 5 03CB 03CC A/D register 6 03CD 03CE A/D register 7...
Page 21: Overview
The M16C/28 Group has normal version, T version, and V version. This hardware manual only describes the normal version. For information on T version and V version, please contact Renesas Technology Corp. 1.1.1 Applications Audio, cameras, office equipment, communication equipment, portable equipment, home appliances (in- verter solution), motor control, industrial equipment, etc.
Page 22: Specifications
1. Overview 1.1.2 Specifications Table 1.1 and 1.2 list specification outline. Table 1.1 Specifications (80/85-Pin Package) Item Function Specification Number of basic instructions 91 instructions Minimum instruction 41.7 ns (f(BCLK) = 24 MH = 4.2 V to 5.5 V) (M16C/28B) excution time 50 ns (f(BCLK) = 20 MH = 3.0 V to 5.5 V) (M16C/28,M16C/28B)
Page 23 1. Overview Table 1.2 Specifications (64-Pin Package) Item Function Specification Number of basic instructions 91 instructions Minimum instruction 41.7 ns (f(BCLK) = 24 MHz, VCC = 4.2 V to 5.5 V) (M16C/28B) excution time 50 ns (f(BCLK) = 20 MHz, VCC = 3.0 V to 5.5 V) (M16C/28,M16C/28B) 100 ns (f(BCLK) = 10 MHz, VCC = 2.7 V to 5.5 V) (M16C/28,M16C/28B) Operation mode Single chip mode...
Page 24: Block Diagram
1. Overview 1.2 Block Diagram Figure 1.1 is a block diagram of the M16C/28 Group, 80-pin and 85-pin packages. Figure 1.2 is a block diagram of the M16C/28 Group, 64-pin package. I/O Ports Port P3 Port P0 Port P1 Port P2 Internal Peripheral Functions Timer (16 bits) UART/clock synchronous SI/O...
Page 25 1. Overview I/O Ports Port P3 Port P0 Port P1 Port P2 Internal Peripheral Functions Timer (16 bits) UART/Clock synchronous SI/O System clock generator (8 bits x 3 channels) Output (Timer A) : 5 Input (Timer B) : 3 Clock synchronous SI/O COUT On-chip oscillator (8 bits x 1 channel)
Page 26: Product Information
1. Overview 1.3 Product Information Tables 1.3 and 1.4 list the M16C/28 Group product information and Figure 1.3 shows the product number- ing system. The specifications are partially different between normal-ver.and T/ V-ver.. Table 1.3 M16C/28 Group Product List -Normal-ver. As of January, 2007 y t i y t i...
Page 27 1. Overview Part No. M 3 0 2 8 0 F C B H P - U 7 Product code Package type: HP : Package PLQP0080KB-A(80P6Q-A) PLQP0064KB-A(64P6Q-A) WG : Package PTLG0085JB-A(85F0G) Version (no): M16C/28 B: M16C/28B ROM capacity / RAM capacity (48K+4K) bytes / 4K bytes 8 : (64K + 4K) bytes / 4K bytes A : (96K + 4K) bytes / 8K bytes...
Page 28 1. Overview Table 1.5 Product Code (Flash Memory Version) - M16C/28 Normal Version, 64-, 80-, and 85-Pin Packages C º C º C º C º C º C º C º C º NOTE: 1. The lead contained products, D3, D5, D7 and D9, are put together with U3, U5, U7 and U9 respectively. Lead-free (Sn-Ag-Cu plating) products can be mounted by both conventional Sn-Pb paste and Lead- free paste.
Page 29 1. Overview (1) Flash Memory Version, PTLG0085JB-A (85F0G), Normal-ver. M30280FA Type No. M30280FAWG B U5 Chip version and product code B : Chip version. XXXXXXX The first edition is shown to be blank and continues with A, B, and C. U5 : Product code.
Page 30: Pin Assignment
1. Overview 1.4 Pin Assignment Figures 1.5 to 1.7 show the pin Assignments (top view). (11) (Vss) (11) (Vss) (11) (Vss) (11) AVss (Vss) AVcc RESET CNVss COUT NOTES: 1. The numbers in each grid (circle) show the pin numbers of the M30280FAHP (PLQP0080KB-A (80P6Q-A)) 2.
Page 31 1. Overview Table 1.8 Pin Characteristics for 85-Pin Package - i t page 11...
Page 32 1. Overview Table 1.8 Pin Characteristics for 85-Pin Package (continued) - i t page 12...
Page 33 1. Overview /AN0 /CLK /AN0 /AN0 /SIN /AN0 /SOUT /AN0 M16C/28 Group /AN0 /AN0 (M16C/28, M16C/28B) /CTS /RTS /CTS /CLKS /CLK PLQP0080KB-A (80P6Q-A) /RxD (Top View) /TXD /SDA /TA0 /CTS1/RTS1/CTS /CLKS /RXD /SCL /TA0 /CLK1 /CLK /TA1 /V/RxD1 /CTS /RTS /TA1 /V/TxD1 AVcc...
Page 34 1. Overview Table 1.9 Pin Characteristics for 80-Pin Package - i t page 14...
Page 35 1. Overview Table 1.9 Pin Characteristics for 80-Pin Package (continued) - i t page 15...
Page 36 1. Overview /AN0 /CLK /AN0 /AN0 OUT3 M16C/28 Group /CTS /RTS /CTS0/CLKS1 /CLK (M16C/28, M16C/28B) /RxD /TxD /TxD /SDA /TA0 /RTS1/CTS1/CTS0/CLKS1 PLQP0064KB-A (64P6Q-A) /RxD /SCL /TA0 /CLK1 /CLK /TA1 /V/RxD1 (Top View) /CTS /RTS /TA1 /V/TxD1 /TA2 /TA2 /AN2 /TA3 /TB2 /TA3 NOTES:...
Page 37 1. Overview Table 1.10 Pin Characteristics for 64-Pin Package - t l page 17...
Page 38 1. Overview Table 1.10 Pin Characteristics for 64-Pin Package (continued) - i t page 18...
Page 39: Pin Description
1. Overview 1.5 Pin Description Table 1.11 Pin Description (64-pin, 80-pin and 85-pin packages) Classification Symbol I/O Type Function Power Supply Apply 2.7 to 5.5V to the Vcc pin. Apply 0V to the Vss pin. Analog Power Supplies power to the A/D converter. Connect the AV pin to V Supply the AV...
Page 40 1. Overview Table 1.11 Pin Description (64-pin, 80-pin and 85-pin packages) (Continued) Classification Symbol I/O Type Function INPC1 to INPC1 Input pins for the time measurement function Timer S OUTC1 to OUTC1 Output pins for the waveform generating function to P0 CMOS I/O ports which have a direction register determines an individual I/O Ports to P1...
Page 41 1. Overview Table 1.11 Pin Description (80-pin and 85-pin packages only) (Continued) Classification Symbol I/O Type Function Serial I/O CLK4 Inputs and outputs the transfer clock Inputs serial data Outputs serial data OUT4 A/D Converter to AN0 Analog input pins for the A/D converter to AN2 to AN2 I/O Ports...
Page 42: Central Processing Unit (Cpu)
2. Central Processing Unit(CPU) 2. Central Processing Unit (CPU) Figure 2.1 shows the CPU registers. The register bank is comprised of 7 registers (R0, R1, R2, R3, A0, A1 and FB) out of 13 CPU registers. Two sets of register banks are provided. b8 b7 R0H(R0's high bits) R0L(R0's low bits)
Page 43: Frame Base Register (Fb)
2. Central Processing Unit(CPU) 2.3 Frame Base Register (FB) FB is configured with 16 bits, and is used for FB relative addressing. 2.4 Interrupt Table Register (INTB) INTB is configured with 20 bits, indicating the start address of an interrupt vector table. 2.5 Program Counter (PC) PC is configured with 20 bits, indicating the address of an instruction to be executed.
Page 44: Memory
3. Memory 3. Memory Figure 3.1 is a memory map of the M16C/28 Group. M16C/28 Group provides 1-Mbyte address space from addresses 00000 to FFFFF . The internal ROM is allocated lower addresses beginning with address FFFFF . For example, 64 Kbytes internal ROM is allocated addresses F0000 to FFFFF Two 2-Kbyte internal ROM areas, block A and block B, are available in the flash memory version.
Page 45: Special Function Register (Sfr)
4. Special Function Register (SFR) 4. Special Function Register (SFR) SFR (Special Function Register) is the control register of peripheral functions. Tables 4.1 to 4.7 list the SFR information. Table 4.1 SFR Information(1) Address Register Symbol After Reset 0000 0001 0002 0003 Processor mode register 0...
Page 46 4. Special Function Register (SFR) Table 4.2 SFR Information(2) Register After Reset Address Symbol 0040 0041 0042 0043 0044 INT3 interrupt control register INT3IC XX00X000 0045 IC/OC 0 interrupt control register ICOC0IC XXXXX000 1 interrupt control register, I 2 C bus interface interrupt control register 0046 IC/OC ICOC1IC, IICIC...
Page 47 4. Special Function Register (SFR) Table 4.3 SFR Information(3) Register Symbol After Reset Address 01B0 01B1 01B2 01B3 Flash memory control register 4 FMR4 01000000 01B4 01B5 Flash memory control register 1 FMR1 000XXX0X 01B6 01B7 Flash memory control register 0 FMR0 00000001 01B8...
Page 48 4. Special Function Register (SFR) Table 4.4 SFR Information(4) Register Symbol After Reset Address 0300 TM, WG register 0 G1TM0, G1PO0 0301 0302 TM, WG register 1 G1TM1, G1PO1 0303 0304 TM, WG register 2 G1TM2, G1PO2 0305 0306 TM, WG register 3 G1TM3, G1PO3 0307 0308...
Page 49 4. Special Function Register (SFR) Table 4.5 SFR Information(5) Register Symbol After Reset Address 0340 0341 0342 Timer A1-1 register TA11 0343 0344 Timer A2-1 register TA21 0345 0346 Timer A4-1 register TA41 0347 0348 Three-phase PWM control register 0 INVC0 0349 Three-phase PWM control register 1...
Page 50 4. Special Function Register (SFR) Table 4.6 SFR Information(6) Register Symbol After Reset Address Count start flag TABSR 0380 Clock prescaler reset flag CPSRF 0XXXXXXX 0381 One-shot start flag ONSF 0382 Trigger select register TRGSR 0383 Up-down flag 0384 0385 Timer A0 register 0386 0387...
Page 51 4. Special Function Register (SFR) Table 4.7 SFR Information(7) Address Register Symbol After Reset 03C0 A/D register 0 03C1 03C2 A/D register 1 03C3 03C4 A/D register 2 03C5 A/D register 3 03C6 03C7 03C8 A/D register 4 03C9 03CA A/D register 5 03CB A/D register 6...
Page 52: Reset
5. Reset 5. Reset Hardware reset, software reset, watchdog timer reset and oscillation stop detection reset are available to initialize the microcomputer. 5.1 Hardware Reset There are two types of hardware resets: a hardware reset 1 and a hardware reset 2. 5.1.1 Hardware Reset 1 ____________ ____________...
Page 53: Software Reset
5. Reset Recommended operating voltage RESET RESET Equal to or less Equal to or less than 0.2V than 0.2V More than td(ROC) + td(P-R) Figure 5.1 Example Reset Circuit 5.2 Software Reset When the PM03 bit in the PM0 register is set to “1” (microcomputer reset), the microcomputer has its pins, CPU, and SFR initialized.
Page 54 5. Reset td(P-R) More than td(ROC) RESET CPU clock 28 cycles CPU clock FFFFC Content of reset vector Address FFFFE Figure 5.2 Reset Sequence ____________ Table 5.1 Pin Status When RESET Pin Level is “L” Status Pin name P0 to P3, Input port (high impedance) P6 to P10 0000...
Page 55: Voltage Detection Circuit
5. Reset 5.5 Voltage Detection Circuit Note =5V is assumed in 5.5 Voltage Detection Circuit. The voltage detection circuit has the reset level detection circuit and the low voltage detection circuit. The reset level detection circuit monitors the voltage applied to the V pin.
Page 56 5. Reset V o l t a g e D e t e c t i o n R e g i s t e r 1 ( 2 ) S y m b o l A d d r e s s A f t e r R e s e t 0 0 0 0 0 0 0...
Page 57 5. Reset Low Voltage Detection Interrupt Register S y m b o l A d d r e s s A f t e r R e s e t D 4 I N T 0 0 1 F B i t S y m b o l Bit Name Function Low voltage detection...
Page 58: Low Voltage Detection Interrupt
5. Reset 5.5.1 Low Voltage Detection Interrupt If the D40 bit in the D4INT register is set to "1" (low voltge detection interrupt enabled), a low voltage detection interrupt request is generated when voltage applied to the V pin is above or below Vdet4. The low voltage detection interrupt shares the same interrupt vector with watchdog timer interrupt and oscillation stop, re-oscillation detection interrupt.
Page 59 5. Reset Low voltage detection interrupt generation circuit DF1, DF0 D42 bit is set to “0”(not detected) by writing a “0” in a program. VC27 bit Low voltage detection circuit is set to “0” (low voltage detection D4INT clock(the circuit disabled), the D42 bit is set to clock with which it VC27 “0”.
Page 60: Limitations On Stop Mode
5. Reset 5.5.2 Limitations on Stop Mode The low voltage detection interrupt is immediately generated and the microcomputer exits stop mode if the CM10 bit in the CM1 register is set to “1” under the conditions below. • the VC27 bit in the VCR2 register is set to “1” (low voltage detection circuit enabled) •...
Page 61: Processor Mode
6. Processor Mode 6. Processor Mode The microcomputer supports single-chip mode only. Figures 6.1 and 6.2 show the associated registers. Processor Mode Register 0 Symbol Address After Reset 0004 Bit Symbol Bit Name Function Reserved bit Set to "0" (b2-b0) The microcomputer is reset when PM03 Software reset bit...
Page 62 6. Processor Mode Processeor Mode Register 2 Symbol Address After Reset 001E XXX00000 Bit Symbol Bit Name Function Specifying wait when 0: 2 wait PM20 accessing SFR during PLL 1: 1 wait operation 0: Clock is protected by PRCR PM21 (3,4) register System clock protective bit...
Page 63 6. Processor Mode The internal bus consists of CPU bus, memory bus, and peripheral bus. Bus Interface Unit (BIU) is used to interfere with CPU, ROM/RAM, and perpheral functions by controling CPU bus, memory bus, and periph- eral bus. Figure 6.3 shows the block diagram of the internal bus. CPU address bus Memory address bus CPU data bus...
Page 64: Clock Generation Circuit
7. Clock Generation Circuit 7. Clock Generation Circuit The clock generation circuit contains four oscillator circuits as follows: (1) Main clock oscillation circuit (2) Sub clock oscillation circuit (3) Variable on-chip oscillators (4) PLL frequency synthesizer Table 7.1 lists the clock generation circuit specifications. Figure 7.1 shows the clock generation circuit. Figures 7.2 to 7.7 show the clock- associated registers.
Page 65 7. Clock Generation Circuit Sub-clock generating circuit COUT 1/32 CM04 PCLK0=1 Sub-clock PCLK0=0 Variable On-chip CM21 on-chip oscillator clock oscillator Oscillation 1SIO stop, re- PCLK1=1 oscillation 2SIO detection PCLK1=0 circuit 8SIO CM10=1(stop mode) frequency 32SIO synthesizer D4INT clock CM07 CM21=1 Main clock CPU clock...
Page 66 7. Clock Generation Circuit System Clock Control Register 0 Symbol Address After Reset 0006 01001000 Bit symbol Bit name Function Reserved bits Set to "0" (b1-b0) Wait Mode peripheral function 0 : Do not stop peripheral function clock in wait mode CM02 (10) clock stop bit...
Page 67 7. Clock Generation Circuit System Clock Control Register 1 Symbol Address After Reset 0007 00100000 Bit Symbol Function Name All clock stop control bit 0 : Clock on CM10 (4, 6) 1 : All clocks off (stop mode) System clock select bit 1 CM11 0 : Main clock (6, 7)
Page 68 7. Clock Generation Circuit Oscillation Stop Detection Register Symbol Address After Reset 000C 2 (11) 0X000010 Bit Symbol Bit Name Function 0: Oscillation stop, re-oscillation Oscillation stop, re- CM20 oscillation detection bit detection function disabled (7, 9, 10, 11) 1: Oscillation stop, re-oscillation detection function enabled 0: Main clock or PLL clock System clock select bit 2...
Page 69 7. Clock Generation Circuit Peripheral Clock Select Register Symbol Address After Reset 0 0 0 0 0 0 PCLKR 025E 00000011 Bit Symbol Bit Name Function Timers A, B clock select bit 0: f (Clock source for Timers A, 1: f PCLK0 B, Timer S, the dead time timer, SI/O3, SI/O4,multi-...
Page 70 7. Clock Generation Circuit PLL Control Register 0 (1,2) Symbol Address After Reset PLC0 001C 0001 X010 Bit Name Function Symbol b1b0 PLL multiplying factor PLC00 0 0 0: Do not set select bit 0 0 1: Multiply by 2 0 1 0: Multiply by 4 0 1 1: PLC01...
Page 71: Main Clock
7. Clock Generation Circuit The following describes the clocks generated by the clock generation circuit. 7.1 Main Clock The main clock is generated by the main clock oscillation circuit. This clock is used as the clock source for the CPU and peripheral function clocks. The main clock oscillator circuit is configured by connecting a resonator between the X and X pins.
Page 72: Sub Clock
7. Clock Generation Circuit 7.2 Sub Clock The sub clock is generated by the sub clock oscillation circuit. This clock is used as the clock source for the CPU clock, as well as the timer A and timer B count sources. The sub clock oscillator circuit is configured by connecting a crystal resonator between the X and X COUT...
Page 73: On-Chip Oscillator Clock
7. Clock Generation Circuit 7.3 On-chip Oscillator Clock This clock is supplied by a variable on-chip oscillator. This clock is used as the clock source for the CPU and peripheral function clocks. In addition, if the PM22 bit in the PM2 register is “1” (on-chip oscillator clock for the watchdog timer count source), this clock is used as the count source for the watchdog timer (Refer to 10.3 Count source protective mode, Watchdog Timer).
Page 74 7. Clock Generation Circuit START Set the CM07 bit to “0” (main clock), the CM17 to CM16 bits to “00 ”(main clock undivided), and the CM06 bit to “0” (CM16 and CM17 bits enabled). Set the PLC02 to PLC00 bits (multiplying factor). (To select a 16 MHz or higher PLL clock) Set the PM20 bit to “0”...
Page 75: Cpu Clock And Peripheral Function Clock
7. Clock Generation Circuit 7.5 CPU Clock and Peripheral Function Clock The CPU clock is used to operate the CPU and peripheral function clocks are used to operate the periph- eral functions. 7.5.1 CPU Clock This is the operating clock for the CPU and watchdog timer. The clock source for the CPU clock can be chosen to be the main clock, sub clock, on-chip oscillator clock or the PLL clock.
Page 76: Power Control
7. Clock Generation Circuit 7.6 Power Control There are three power control modes. In this Chapter, all modes other than wait and stop modes are referred to as normal operation mode here. 7.6.1 Normal Operation Mode Normal operation mode is further classified into seven modes. In normal operation mode, because the CPU clock and the peripheral function clocks both are on, the CPU and the peripheral functions are operating.
Page 77: Wait Mode
7. Clock Generation Circuit 7.6.1.6 On-chip Oscillator Mode The selected on-chip oscillator clock divided by 1 (undivided), 2, 4, 8 or 16 provides the CPU clock. The on-chip oscillator clock is also the clock source for the peripheral function clocks. If the sub clock is on, f can be used as the count source for timers A and B.
Page 78 7. Clock Generation Circuit 7.6.2.3 Pin Status During Wait Mode The I/O port pins retain their status held just prior to wait mode. 7.6.2.4 Exiting Wait Mode ______ The microcomputer is moved out of wait mode by a hardware reset, NMI interrupt or peripheral func- tion interrupt.
Page 79: Stop Mode
7. Clock Generation Circuit 7.6.3 Stop Mode In stop mode, all oscillator circuits are turned off, so are the CPU clock and the peripheral function clocks. Therefore, the CPU and the peripheral functions clocked by these clocks stop operating. The least amount of power is consumed in this mode.
Page 80 7. Clock Generation Circuit Figure 7.11 shows the state transition from normal operation mode to stop mode and wait mode. Figure 7.12 shows the state transition in normal operation mode. Table 7.5 shows a state transition matrix describing allowed transition and setting. The vertical line shows current state and horizontal line shows state after transition.
Page 81 7. Clock Generation Circuit Main clock oscillation On-chip oscillator clock oscillation On-chip oscillator low power Middle-speed mode Middle-speed mode Middle-speed mode PLL operation mode Middle-speed mode On-chip oscillator mode PLC07=1 dissipation mode (divide by 4) (divide by 8) (divide by 16) High-speed mode (divide by 2) CM11=1...
Page 82 7. Clock Generation Circuit Table 7.5 Allowed Transition and Setting State after transition On-chip oscillator On-chip oscillator High-speed mode, Low-speed mode 2 Low power PLL operation low power Stop mode mode 2 Wait mode mode middle-speed mode dissipation mode dissipation mode (9) 7 (13) 3 (16) 1...
Page 83: System Clock Protective Function
7. Clock Generation Circuit 7.7 System Clock Protective Function When the main clock is selected for the CPU clock source, this function protects the clock from modifica- tions in order to prevent the CPU clock from becoming halted by run-away. If the PM21 bit in the PM2 register is set to “1”...
Page 84: Operation When Cm27 Bit Is Set To "0" (Oscillation Stop Detection Reset)
7. Clock Generation Circuit 7.8.1 Operation when CM27 bit is set to "0" (Oscillation Stop Detection Reset) When main clock stop is detected when the CM20 bit is “1” (oscillation stop, re-oscillation detection function enabled), the microcomputer is initialized, coming to a halt (oscillation stop reset; refer to 4. SFR and 5.
Page 85: How To Use Oscillation Stop And Re-Oscillation Detect Function
7. Clock Generation Circuit 7.8.3 How to Use Oscillation Stop and Re-oscillation Detect Function • The oscillation stop and re-oscillation detect interrupt shares the vector with the watchdog timer inter- rupt. If the oscillation stop, re-oscillation detection and watchdog timer interrupts both are used, read the CM22 bit in an interrupt routine to determine which interrupt source is requesting the interrupt.
Page 86: Protection
8. Protection 8. Protection In the event that a program runs out of control, this function protects the important registers so that they will not be rewritten easily. Figure 8.1 shows the PRCR register. The following lists the registers protected by the PRCR register.
Page 87: Interrupts
9. Interrupts 9. Interrupts Note The SI/O4 interrupt of peripheral function interrupt is not available in the 64-pin package. 9.1 Type of Interrupts Figure 9.1 shows types of interrupts. Undefined instruction (UND instruction) Overflow (INTO instruction) Software BRK instruction (Non-maskable interrupt) INT instruction _______ ________...
Page 88: Software Interrupts
9. Interrupts 9.1.1 Software Interrupts A software interrupt occurs when executing certain instructions. Software interrupts are non-maskable interrupts. 9.1.1.1 Undefined Instruction Interrupt An undefined instruction interrupt occurs when executing the UND instruction. 9.1.1.2 Overflow Interrupt An overflow interrupt occurs when executing the INTO instruction with the O flag set to “1” (the opera- tion resulted in an overflow).
Page 89: Hardware Interrupts
9. Interrupts 9.1.2 Hardware Interrupts Hardware interrupts are classified into two types — special interrupts and peripheral function interrupts. 9.1.2.1 Special Interrupts Special interrupts are non-maskable interrupts. _______ 9.1.2.1.1 NMI Interrupt _______ _______ An NMI interrupt is generated when input on the NMI pin changes state from high to low. For details _______ _______ about the NMI interrupt, refer to the section 9.7 NMI interrupt.
Page 90: Interrupts And Interrupt Vector
9. Interrupts 9.2 Interrupts and Interrupt Vector One interrupt vector consists of 4 bytes. Set the start address of each interrupt routine in the respective interrupt vectors. When an interrupt request is accepted, the CPU branches to the address set in the corresponding interrupt vector.
Page 91: Relocatable Vector Tables
9. Interrupts 9.2.2 Relocatable Vector Tables The 256 bytes beginning with the start address set in the INTB register comprise a reloacatable vector table area. Table 9.2 lists the relocatable vector tables. Setting an even address in the INTB register results in the interrupt sequence being executed faster than in the case of odd addresses.
Page 92: Interrupt Control
9. Interrupts 9.3 Interrupt Control The following describes how to enable/disable the maskable interrupts, and how to set the priority in which order they are accepted. What is explained here does not apply to nonmaskable interrupts. Use the I flag in the FLG register, IPL, and ILVL2 to ILVL0 bits in each interrupt control register to enable/ disable the maskable interrupts.
Page 93 9. Interrupts Interrupt Control Register Symbol Address After Reset ICOC0 0045 XXXXX000 IC ICOC1IC, IICIC 0046 XXXXX000 BTIC, SCLDAIC 0047 XXXXX000 BCNIC 004A XXXXX000 DM0IC, DM1IC 004B , 004C XXXXX000 KUPIC 004D XXXXX000 ADIC 004E XXXXX000 S0TIC to S2TIC 0051 , 0053 , 004F XXXXX000...
Page 94 9. Interrupts Interrupt Request Cause Select Register Symbol Address After Reset IFSR 035F Bit Symbol Bit Name Function IFSR0 INT0 interrupt polarity 0 : One edge switching bit 1 : Both edges IFSR1 INT1 interrupt polarity 0 : One edge switching bit 1 : Both edges IFSR2...
Page 95: I Flag
9. Interrupts 9.3.1 I Flag The I flag enables or disables the maskable interrupt. Setting the I flag to “1” (enabled) enables the maskable interrupt. Setting the I flag to “0” (disabled) disables all maskable interrupts. 9.3.2 IR Bit The IR bit is set to “1” (interrupt requested) when an interrupt request is generated. Then, when the interrupt request is accepted and the CPU branches to the corresponding interrupt vector, the IR bit is cleared to “0”...
Page 96: Interrupt Sequence
9. Interrupts 9.4 Interrupt Sequence An interrupt sequence (the device behavior from the instant an interrupt is accepted to the instant the interrupt routine is executed) is described here. If an interrupt occurs during execution of an instruction, the processor determines its priority when the execution of the instruction is completed, and transfers control to the interrupt sequence from the next cycle.
Page 97: Interrupt Response Time
9. Interrupts 9.4.1 Interrupt Response Time Figure 9.6 shows the interrupt response time. The interrupt response or interrupt acknowledge time denotes the time from when an interrupt request is generated till when the first instruction in the interrupt routine is executed. Specifically, it consists of the time from when an interrupt request is generated till when the instruction then executing is completed ((a) in Figure 9.6) and the time during which the inter- rupt sequence is executed ((b) in Figure 9.6).
Page 98: Saving Registers
9. Interrupts 9.4.3 Saving Registers In the interrupt sequence, the FLG register and PC are saved to the stack. At this time, the 4 high-order bits of the PC and the 4 high-order (IPL) and 8 low-order bits of the FLG register, 16 bits in total, are saved to the stack first.
Page 99 9. Interrupts The operation of saving registers carried out in the interrupt sequence is dependent on whether the SP at the time of acceptance of an interrupt request, is even or odd. If the stack pointer is even, the FLG register and the PC are saved, 16 bits at a time.
Page 100: Returning From An Interrupt Routine
9. Interrupts 9.4.4 Returning from an Interrupt Routine The FLG register and PC in the state in which they were immediately before entering the interrupt se- quence are restored from the stack by executing the REIT instruction at the end of the interrupt routine. Thereafter the CPU returns to the program which was being executed before accepting the interrupt request.
Page 101 9. Interrupts Priority level of each interrupt Level 0 (initial value) INT1 Highest Timer B2 Timer B0 Timer A3 Timer A1 IC/OC interrupt 1, I C bus interface INT3 INT2 INT0 Timer B1 Timer A4 Timer A2 IC/OC base timer, S IC/OC interrupt 0 UART1 reception UART0 reception...
Page 102: Int Interrupt
9. Interrupts ______ 9.6 INT Interrupt _______ INTi interrupt (i=0 to 5) is triggered by the edges of external inputs. The edge polarity is selected using the IFSRi bit in the IFSR register. ________ The INT5 input has an effective digital debounce function for a noise rejection. Refer to "17.6 Digital ________ Debounce function"...
Page 103: Nmi Interrupt
9. Interrupts ______ 9.7 NMI Interrupt _______ _______ An NMI interrupt request is generated when input on the NMI pin changes state from high to low, after the _______ ______ NMI interrupt was enabled by writing a “1” to bit 4 of register PM2. The NMI interrupt is a non-maskable interrupt, once it is enabled.
Page 104: Address Match Interrupt
9. Interrupts 9.9 Address Match Interrupt An address match interrupt request is generated immediately before executing the instruction at the ad- dress indicated by the RMADi register (i=0 to 1). Set the start address of any instruction in the RMADi register.
Page 105 9. Interrupts Address Match Interrupt Enable Register Symbol Address After Reset AIER 0009 XXXXXX00 Bit Symbol Bit Name Function Address match interrupt 0 0 : Interrupt disabled AIER0 enable bit 1 : Interrupt enabled Address match interrupt 1 AIER1 0 : Interrupt disabled enable bit 1 : Interrupt enabled Nothing is assigned.
Page 106: Watchdog Timer
10. Watchdog Timer 10. Watchdog Timer The watchdog timer is the function that detects when a program is out of control. Use the watchdog timer is recommended to improve reliability of the system. The watchdog timer contains a 15-bit counter which is decremented by the CPU clock that the prescaler divides.
Page 107: Count Source Protective Mode
10. Watchdog Timer Watchdog Timer Control Register Symbol Address After Reset 000F 00XXXXXX Bit Symbol Bit Name Function (b4-b0) High-order bit of watchdog timer Reserved bit Set to “0” (b5) Reserved bit Set to “0” (b6) 0: Divided by 16 WDC7 Prescaler select bit 1: Divided by 128...
Page 108: Dmac
11. DMAC 11. DMAC Note Do not use SI/04 interrupt request as a DMA request in the 64-pin package. The DMAC (Direct Memory Access Controller) allows data to be transferred without the CPU intervention. Two DMAC channels are included. Each time a DMA request occurs, the DMAC transfers one (8 or 16-bit) data from the source address to the destination address.
Page 109 11. DMAC Table 11.1 DMAC Specifications Item Specification No. of channels 2 (cycle steal method) Transfer memory space • From any address in the 1M bytes space to a fixed address • From a fixed address to any address in the 1M bytes space •...
Page 110 11. DMAC DMA0 Request Cause Select Register Symbol Address After Reset DM0SL 03B8 Bit Symbol Bit Name Function DSEL0 DMA request cause Refer to note (1) select bit DSEL1 DSEL2 DSEL3 Nothing is assigned. When write, set to “0”. When read, its content is “0”. (b5-b4) DMA request cause 0: Basic cause of request...
Page 111 11. DMAC DMA1 Request Cause Select Register Symbol Address After Reset DM1SL 03BA Bit Name Function Bit Symbol DSEL0 DMA request cause Refer to note (1) select bit DSEL1 DSEL2 DSEL3 Nothing is assigned. When write, set to “0”. (b5-b4) When read, its content is “0”.
Page 112 11. DMAC DMAi Source Pointer (i = 0, 1) (b19) (b16)(b15) (b8) (b23) Symbol Address After Reset SAR0 0022 to 0020 Indeterminate SAR1 0032 to 0030 Indeterminate Function Setting Range Set the source address of transfer 00000 to FFFFF Nothing is assigned. When write, set “0”. When read, these contents are “0”.
Page 113: Transfer Cycles
11. DMAC 11.1 Transfer Cycles The transfer cycle consists of a memory or SFR read (source read) bus cycle and a write (destination write) bus cycle. The number of read and write bus cycles is affected by the source and destination addresses of transfer.
Page 114 11. DMAC (1) When the transfer unit is 8 or 16 bits and the source of transfer is an even address CPU clock Address Dummy CPU use Source Destination CPU use cycle RD signal WR signal Data Dummy Destination CPU use Source CPU use cycle...
Page 115: Dma Transfer Cycles
11. DMAC 11.2. DMA Transfer Cycles Any combination of even or odd transfer read and write adresses is possible. Table 11.2 shows the number of DMA transfer cycles. Table 11.3 shows the Coefficient j, k. The number of DMAC transfer cycles can be calculated as follows: No.
Page 116: Dma Enable
11. DMAC 11.3 DMA Enable When a data transfer starts after setting the DMAE bit in DMiCON register (i = 0, 1) to “1” (enabled), the DMAC operates as follows: (a) Reload the forward address pointer with the SARi register value when the DSD bit in DMiCON register is “1”...
Page 117: Channel Priority And Dma Transfer Timing
11. DMAC 11.5 Channel Priority and DMA Transfer Timing If both DMA0 and DMA1 are enabled and DMA transfer request signals from DMA0 and DMA1 are de- tected active in the same sampling period (one period from a falling edge to the next falling edge of CPU clock), the DMAS bit on each channel is set to “1”...
Page 118: Timer
12. Timer 12. Timer Eight 16-bit timers, each capable of operating independently of the others, can be classified by function as either timer A (five) and timer B (three). The count source for each timer acts as a clock, to control such timer operations as counting, reloading, etc.
Page 119 12. Timer PCLK0 bit = 0 Clock prescaler • Main clock 1 or 1/32 • PLL clock PCLK0 bit = 1 • On-chip oscillator Reset clock Set the CPSR bit in the CPSRF register to “1” (prescaler reset) 1 or Timer B2 overflow or underflow ( to Timer A count source) •...
Page 120: Timer A
12. Timer 12.1 Timer A Figure 12.3 shows a block diagram of the timer A. Figures 12.4 to 12.6 show registers related to the timer A. The timer A supports the following four modes. Except in event counter mode, timers A0 to A4 all have the same function.
Page 121 12. Timer Timer Ai Register (i= 0 to 4) Symbol Address After Reset (b15) (b8) 0387 , 0386 Indeterminate b0 b7 0389 , 0388 Indeterminate 038B , 038A Indeterminate 038D , 038C Indeterminate 038F , 038E Indeterminate Function Mode Setting Range Timer Divide the count source by n + 1 where n = 0000...
Page 122 12. Timer One-shot Start Flag Symbol Address After Reset ONSF 0382 Bit Symbol Bit Name Function Timer A0 one-shot start flag TA0OS The timer starts counting by setting this bit to “1” while the TMOD1 to Timer A1 one-shot start flag TA1OS TMOD0 bits of TAiMR register (i = 0 to 4) = ‘10...
Page 123: Timer Mode
12. Timer 12.1.1 Timer Mode In timer mode, the timer counts a count source generated internally (see Table 12.1). Figure 12.7 shows TAiMR register in timer mode. Table 12.1 Specifications in Timer Mode Item Specification Count source Count operation • Decrement •...
Page 124: Event Counter Mode
12. Timer 12.1.2 Event Counter Mode In event counter mode, the timer counts pulses from an external device or overflows and underflows of other timers. Timers A2, A3 and A4 can count two-phase external signals. Table 12.2 lists specifications in event counter mode (when not processing two-phase pulse signal). Table 12.3 lists specifications in event counter mode (when processing two-phase pulse signal with the timers A2, A3 and A4).
Page 125 12. Timer Timer Ai Mode Register (i=0 to 4) (When not using two-phase pulse signal processing) Symbol Address After Reset TA0MR to TA4MR 0396 to 039A Bit Symbol Bit Name Function TMOD0 b1 b0 Operation mode select bit 0 1 : Event counter mode TMOD1 0 : Pulse is not output Pulse output function...
Page 126 12. Timer Table 12.3 Specifications in Event Counter Mode (when processing two-phase pulse signal with timers A2, A3 and A4) Item Specification Count source • Two-phase pulse signals input to TAi or TAi pins (i = 2 to 4) Count operation •...
Page 127 12. Timer Timer Ai Mode Register (i=2 to 4) (When using two-phase pulse signal processing) Symbol Address After Reset TA2MR to TA4MR 0398 to 039A Bit Symbol Bit Name Function TMOD0 b1 b0 Operation mode select bit 0 1 : Event counter mode TMOD1 To use two-phase pulse signal processing, set this bit to “0”.
Page 128 12. Timer 12.1.2.1 Counter Initialization by Two-Phase Pulse Signal Processing This function initializes the timer count value to “0” by Z-phase (counter initialization) input during two- phase pulse signal processing. This function can only be used in timer A3 event counter mode during two-phase pulse signal process- ________ ing, free-running type, x4 processing, with Z-phase entered from the INT2 pin.
Page 129: One-Shot Timer Mode
12. Timer 12.1.3 One-shot Timer Mode In one-shot timer mode, the timer is activated only once by one trigger. (See Table 12.4) When the trigger occurs, the timer starts up and continues operating for a given period. Figure 12.11 shows the TAiMR register in one-shot timer mode.
Page 130 12. Timer Timer Ai Mode Register (i=0 to 4) Symbol Address After Reset TA0MR to TA4MR to 039A Bit Symbol Bit Name Function TMOD0 b1 b0 Operation mode select bit 1 0 : One-shot timer mode TMOD1 Pulse output function 0 : Pulse is not output select bit pin functions as I/O port)
Page 131: Pulse Width Modulation (Pwm) Mode
12. Timer 12.1.4 Pulse Width Modulation (PWM) Mode In PWM mode, the timer outputs pulses of a given width in succession (see Table 12.5). The counter functions as either 16-bit pulse width modulator or 8-bit pulse width modulator. Figure 12.12 shows TAiMR register in pulse width modulation mode.
Page 132 12. Timer Timer Ai Mode Register (i= 0 to 4) Symbol Address After Reset TA0MR to TA4MR 0396 to 039A Bit Symbol Bit Name Function TMOD0 b1 b0 Operation mode 1 1 : PWM mode select bit TMOD1 0: Pulse is not output(TAiOUT pin functions as I/O port) Pulse output funcion 1: Pulse is output(TAiOUT pin functions as a pulse select bit...
Page 133 12. Timer 1 / f – 1) Count source “H” Input signal to “L” Trigger is not generated by this signal 1 / f “H” PWM pulse output from TA iOUT “L” IR bit of TAiIC “1” register “0” : Frequency of count source Set to “0”...
Page 134: Timer B
12. Timer 12.2 Timer B Figure 12.15 shows a block diagram of the timer B. Figures 12.16 and 12.17 show registers related to the timer B. Timer B supports the following four modes. Use the TMOD1 and TMOD0 bits in the TBiMR register (i = 0 to 2) to select the desired mode.
Page 135 12. Timer )(1) Timer Bi Register (i=0 to 2 Symbol Address After Reset 0391 , 0390 Undefined (b15 (b8) b0 b7 0393 , 0392 Undefined 0395 , 0394 Undefined Setting Rrange Function Mode Divide the count source by n + 1 0000 to FFFF Timer mode...
Page 136: Timer Mode
12. Timer 12.2.1 Timer Mode In timer mode, the timer counts a count source generated internally (see Table 12.6). Figure 12.18 shows TBiMR register in timer mode. Table 12.6 Specifications in Timer Mode Item Specification Count source Count operation • Decrement •...
Page 137: Event Counter Mode
12. Timer 12.2.2 Event Counter Mode In event counter mode, the timer counts pulses from an external device or overflows and underflows of other timers (see Table 12.7) . Figure 12.19 shows the TBiMR register in event counter mode. Table 12.7 Specifications in Event Counter Mode Item Specification Count source...
Page 138: Pulse Period And Pulse Width Measurement Mode
12. Timer 12.2.3 Pulse Period and Pulse Width Measurement Mode In pulse period and pulse width measurement mode, the timer measures pulse period or pulse width of an external signal (see Table 12.8). Figure 12.20 shows the TBiMR register in pulse period and pulse width measurement mode.
Page 139 12. Timer Count source “H” Measurement pulse “L” Transfer Transfer (indeterminate value) (measured value) Reload register counter transfer timing Timing at which counter reaches “0000 ” “1” TBiS bit “0” “1” TBiIC register's IR bit “0” Set to “0” upon accepting an interrupt request or by program “1”...
Page 140: A/D Trigger Mode
12. Timer 12.2.4 A/D Trigger Mode A/D trigger mode is used together with simultaneous sample sweep mode or delayed trigger mode 0 of A/D conversion to start A/D conversion. It is used in timer B0 and timer B1 only. In this mode, the timer starts counting by one trigger until the count value becomes 0000 .
Page 141 12. Timer Timer Bi Mode Register (i= 0 to 1) Symbol Address After Reset TB0MR to TB1MR 039B to 039C 00XX0000 Bit Symbol Bit Name Function TMOD0 b1 b0 Operation mode select bit 0 0 : Timer mode or A/D trigger mode TMOD1 Invalid in A/D trigger mode Either "0"...
Page 142: Three-Phase Motor Control Timer Function
12. Timer 12.3 Three-phase Motor Control Timer Function Timers A1, A2, A4 and B2 can be used to output three-phase motor drive waveforms. Table 12.10 lists the specifications of the three-phase motor control timer function. Figure 12.24 shows the block diagram for three- phase motor control timer function.
Page 143 12. Timer Figure 12.25 Three-phase Motor Control Timer Functions Block Diagram page 123...
Page 144 12. Timer Three-phase PWM Control Register 0 b7 b6 b5 b4 b3 b2 b1 b0 Symbol Address After Reset INVC0 0348 Bit Symbol Bit Name Function Effective interrupt output 0: ICTB2 counter is incremented by 1 on INV00 polarity select bit the rising edge of timer A1 reload control signal 1: ICTB2 counter is incremented by 1 on...
Page 145 12. Timer Three-phase PWM Control Register 1 b7 b6 b5 b4 b3 b2 b1 b0 Symbol Address After Reset INVC1 0349 Bit Symbol Bit Name Function Timer A1, A2, A4 start 0: Timer B2 underflow INV10 trigger signal select bit 1: Timer B2 underflow and write to the TB2 register Timer A1-1, A2-1, A4-1...
Page 146 12. Timer Three-phase Output Buffer Register(i=0,1) Symbol Address After Reset IDB0 034A 00111111 IDB1 034B 00111111 Bit Symbol Bit Name Function Write the output level U phase output buffer i 0: Active level 1: Inactive level DUBi U phase output buffer i When read, these bits show the three-phase V phase output buffer i output shift register value.
Page 147 12. Timer (1, 2, 3, 4, 5) Timer Ai, Ai-1 Register (i=1, 2, 4) Symbol Address After reset 0389 -0388 Indeterminate 038B -038A Indeterminate (b15) (b8) 038F -038E Indeterminate b0 b7 (6,7) TA11 0343 -0342 Indeterminate (6,7) TA21 0345 -0344 Indeterminate (6,7) TA41...
Page 148 12. Timer Timer B2 Special Mode Register Symbol Address After Reset TB2SC 039E X0000000 Bit Symbol Bit Name Function PWCON Timer B2 reload timing 0: Timer B2 underflow switch bit 1: Timer A output at odd-numbered Three-phase output port 0: Three-phase output forcible cutoff by SD pin input IVPCR1 SD control bit 1 (high impedance) disabled...
Page 149 12. Timer Timer B2 Register (b15) (b8) b0 b7 Symbol Address After Reset 0395 -0394 Indeterminate Setting Range Function 0000 to FFFF Divide the count source by n + 1 where n = set value. Timer A1, A2 and A4 are started at every occurrence of underflow.
Page 150 12. Timer Timer Ai Mode Register Symbol Address After Reset b7 b6 b5 b4 b3 b2 b1 b0 TA1MR 0397 TA2MR 0398 TA4MR 039A Bit Symbol Bit Name Function TMOD0 Set to “10 ” (one-shot timer mode) for the Operation mode three-phase motor control timer function select bit TMOD1...
Page 151 12. Timer The three-phase motor control timer function is enabled by setting the INV02 bit in the INVC0 register to “1”. When this function is on, timer B2 is used to control the carrier wave, and timers A4, A1 and A2 are used to control three-phase PWM outputs (U, U, V, V, W and W).
Page 152 12. Timer Sawtooth Waveform as a Carrier Wave Sawtooth wave Signal wave Timer B2 Start trigger signal for timer A4 Timer A4 one-shot pulse Rewrite registers Transfer the values to the three- IDB0 and IDB1 phase output shift register U phase output signal U phase output signal...
Page 153: Position-Data-Retain Function
12. Timer 12.3.1 Position-Data-Retain Function This function is used to retain the position data synchronously with the three-phase waveform output.There are three position-data input pins for U, V, and W phases. A trigger to retain the position data (hereafter, this trigger is referred to as "retain trigger") can be selected by the PDRT bit in the PDRF register.
Page 154 12. Timer 12.3.1.2 Position-data-retain Function Control Register Figure 12.36 shows the structure of the position-data-retain function contol register. Position-data-retain Function Control Register Symbol Address After Reset PDRF 034E XXXX 0000 Bit Symbol Bit Name Function Input level at pin IDW is read out. W-phase position PDRW 0: "L"...
Page 155: Timer S
13. Timer S 13. Timer S The Timer S (Input Capture/Output Compare : here after, Timer S is referred to as "IC/OC".) is a high- performance I/O port for time measurement and waveform generation. The IC/OC has one 16-bit base timer for free-running operation and eight 16-bit registers for time measure- ment and waveform generation.
Page 156 13. Timer S Figure 13.1 shows the block diagram of the IC/OC. PCLK0=0 Main clock, PLL clock, or f On-chip PCLK0=1 oscillator clock Request by matching G1BTRR and base timer Request by matching G1PO0 register and base timer Request from INT1 pin Base timer reset BCK1 to BCK0 or f...
Page 157 13. Timer S Figures 13.2 to 13.10 show registers associated with the IC/OC base timer, the time measurement func- tion, and the waveform generating function. Base Timer Register (b7) (b0) Symbol Address After Reset G1BT 0321 - 0320 Indeterminate Setting Range Function When the base timer is operating: When read, the value of base timer plus 1 can...
Page 158 13. Timer S Divider Register Symbol Address After Reset G1DV 032A Function Setting range Divide f or two-phase pulse input by (n+1) to FF for f clock cycles generation. n: the setting value of the G1DV register Base Timer Control Register 1 Symbol Address After Reset...
Page 159 13. Timer S Base Timer Reset Register (b7) (b0) Symbol Address After Reset G1BTRR 0329 - 0328 Indeterminate Function Setting Range When enabled by the RST4 bit in the G1BCR0 0000 to FFFF register, the base timer is reset by matching the G1BTRR register setting value and the base timer setting value.
Page 160 13. Timer S Time Measurement Control Register j (j=0 to 7) Symbol Address After Reset G1TMCR0 to G1TMCR3 0318 , 0319 , 031A , 031B G1TMCR4 to G1TMCR7 031C , 031D , 031E , 031F Bit Name Function Symbol CTS0 : No time measurement Time Measurement : Rising edge...
Page 161 13. Timer S Waveform Generation Register j (j=0 to 7) Symbol Address After Reset (b0) (b7) G1TM0 to G1TM2 0301 -0300 0303 -0302 0305 -0304 Indeterminte G1TM3 to G1TM5 0307 -0306 0309 -0308 030B -030A Indeterminte Indeterminte G1TM6 to G1TM7 030D -030C 030F...
Page 162 13. Timer S Waveform Generation Register j (j=0 to 7) Symbol Address After Reset (b0) (b7) G1PO0 to G1PO2 0301 -0300 0303 -0302 0305 -0304 Indeterminate G1PO3 to G1PO5 0307 -0306 0309 -0308 030B -030A Indeterminate Indeterminate G1PO6 to G1PO7 030D -030C 030F...
Page 163 13. Timer S Function Select Register Symbol Address After Reset G1FS 0327 Bit Name Function Symbol Channel 0 Time Measure- 0 : Select the waveform generating FSC0 ment/Waveform Generating Function Select Bit function 1 : Select the time measurement Channel 1 Time Measure- FSC1 ment/Waveform Generating function...
Page 164: Interrupt Request Register
13. Timer S Interrupt Request Register Symbol Address After Reset G1IR 0330 Indeterminate Bit Name Function Symbol 0 : No interrupt request G1IR0 Interrupt Request, Ch0 1 : Interrupt requested G1IR1 Interrupt Request, Ch1 G1IR2 Interrupt Request, Ch2 G1IR3 Interrupt Request, Ch3 G1IR4 Interrupt Request, Ch4 G1IR5...
Page 165 13. Timer S Interrupt Enable Register 0 Symbol Address After Reset G1IE0 0331 Bit Name Function Symbol 0 : IC/OC interrupt 0 request disable G1IE00 Interrupt Enable 0, CH0 1 : IC/OC interrupt 0 request enable G1IE01 Interrupt Enable 0, CH1 G1IE02 Interrupt Enable 0, CH2 G1IE03...
Page 166: Base Timer
13. Timer S 13.1 Base Timer The base timer is a free-running counter that counts an internally generated count source. Table 13.2 lists specifications of the base timer. Table 13.3 shows registers associated with the base timer. Figure 13.11 shows a block diagram of the base timer. Figure 13.12 shows an example of the base timer in counter increment mode.
Page 167 13. Timer S BCK1 to BCK0 or f (n+1) divider Base timer b14 b15 Two-phase pulse input (Note 1) Overflow signal Base timer BTS bit in G1BCR1 register overflow request RST4 Matched with G1BTRR RST1 Base timer reset Matched with G1PO0 register RST2 NOTES: Input "L"...
Page 168 13. Timer S FFFF C000 State of a counter 8000 4000 0000 IT=1 in the G1BCR0 register (Base timer interrupt generated by the bit 14 overflow) "1" b14 overflow signal "0" Base Timer interrupts IT=0 in the G1BCR0 register (Base timer interrupt generated by the bit 15 overflow) "1"...
Page 169 13. Timer S (1) When the base timer is reset while the base timer increments the counter (A-phase) Input waveform min 1 µs min 1 µs (B-phase) When selects no division with the divider by (n+1) (Note 1) INT1 (Z-phase) Base timer starts counting Value of counter Set to "0"...
Page 170: Base Timer Reset Register(G1Btrr)
13. Timer S 13.1.1 Base Timer Reset Register(G1BTRR) The G1BTRR register provides the capability to reset the base timer when the base timer count value matches the value stored in the G1BTRR register. The G1BTRR register is enabled by the RST4 bit in the G1BCR0 register.
Page 171: Interrupt Operation
13. Timer S 13.2 Interrupt Operation The IC/OC interrupt contains several request causes. Figure 13.18 shows the IC/OC interrupt block dia- gram and Table 13.4 shows the IC/OC interrupt assignation. When either the base timer reset request or base timer overflow request is generated, the IR bit in the BTIC register corresponding to the IC/OC base timer interrupt is set to "1"...
Page 172: Time Measurement Function
13. Timer S 13.4 Time Measurement Function In synchronization with an external trigger input, the value of the base timer is stored into the G1TMj register (j=0 to 7). Table 13.5 shows specifications of the time measurement function. Table 13.6 shows register settings associated with the time measurement function.
Page 173 13. Timer S Table 13.6 Register Settings Associated with the Time Measurement Function Register Function G1TMCRj CTS1 to CTS0 Select time measurement trigger DF1 to DF0 Select the digital filter function GT, GOC, GSC Select the gate function Select the prescaler function G1TPRk Setting value of prescaler G1FS...
Page 174 13. Timer S When selecting the rising edge as a timer measurement trigger (The CTS1 to CTS0 bits in the G1TMCR register (j=0 to 7)=01 Base timer n+9 n+10 n+11 n+12 n+13 n+14 INPC1j pin input or trigger signal after passing the digital filter G1IRj bit...
Page 175 13. Timer S (a) With the prescaler function (When the G1TPRj register (j = 6,7) is set to "02 ", the PR bit in the G1TMCRj (j = 6,7) register is set to "1") Base timer n+9 n+10 n+11 +12 n+13 n+14 INPC1j pin input or trigger signal after...
Page 176: Waveform Generating Function
13. Timer S 13.5 Waveform Generating Function Waveforms are generated when the base timer value matches the G1POj (j=0 to 7) register value. The waveform generating function has the following three modes : • Single-phase waveform output mode • Phase-delayed waveform output mode •...
Page 177: Single-Phase Waveform Output Mode
13. Timer S 13.5.1 Single-Phase Waveform Output Mode Output signal level of the OUTC1j pin becomes high("H") when the INV bit in the G1POCRj (j=0 to 7) register is set to "0"(output is not reversed) and the base timer value matches the G1POj (j=0 to 7) register value.
Page 178 13. Timer S (1) Free-running operation (The RST4, RST2, and RST1 bits in the G1BCR0 and G1BCR1 registers are set to "0") FFFF Base timer 0000 65536-m Inverse Inverse OUTC1j pin Return to default output level 65536 When setting to "0", write "0"...
Page 179: Phase-Delayed Waveform Output Mode
13. Timer S 13.5.2 Phase-Delayed Waveform Output Mode Output signal level of the OUTC1j pin is inversed every time the base timer value matches the G1POj register value ( j=0 to 7). Table 13.9 lists specifications of phase-delayed waveform mode. Figure 13.23 shows an example of phase-delayed waveform mode operation.
Page 180 13. Timer S (1) Free-running operation (The RST4, RST2, and RST1 bits in the G1BCR0 and G1BCR1 registers are set to "0") FFFF Base timer 0000 65536 65536 Inverse OUTC1j pin Inverse 65536X2 Write "0" by program if setting to "0" G1IRj bit j=0 to 7 m : Setting value of the G1POj register...
Page 181: Set/Reset Waveform Output (Sr Waveform Output) Mode
13. Timer S 13.5.3 Set/Reset Waveform Output (SR Waveform Output) Mode Output signal level of the OUTC1j pin becomes high ("H") when the INV bit in the G1POCRi (i=0 to 7) is set to "0" (output is not reversed) and the base timer value matches the G1POj register value (j=0, 2, 4, 6). The "H"...
Page 182 13. Timer S (1) Free-running operation (Bits RST2 and RST1 in the G1BCR0 register and the RST4 bit in the G1BCR1 register are set to 0) FFFF Base timer 0000 65536-n+m Return to default output level OUTC1j pin Inverse Inverse 65536 Write 0 by program if setting to 0...
Page 183: I/O Port Function Select
13. Timer S 13.6 I/O Port Function Select The value in the G1FE and G1FS registers decides which IC/OC pin to be an input or output pin. In SR waveform generating mode, two channels, a set of even channel and odd channel, are used every output waveform, however, the waveform is output from an even channel only.
Page 184: Inpc17 Alternate Input Pin Selection
13. Timer S 13.6.1 INPC17 Alternate Input Pin Selection The input capture pin for IC/OC channel 7 can be assigned to one of two package pins. The CH7INSEL ________ bit in the G1BCR0 register selects IC/OC INPC1 from P2 /OUTC1 /INPC1 or P17/INT5/INPC1 /IDU.
Page 185: Serial I/O
14. Serial I/O 14. Serial I/O Note The SI/O4 interrupt of peripheral function interrupt is not available in the 64-pin package. Serial I/O is configured with five channels: UART0 to UART2, SI/O3 and SI/O4. 14.1 UARTi (i=0 to 2) UARTi each have an exclusive timer to generate a transfer clock, so they operate independently of each other.
Page 186 14.Serial I/O PCLK1=0 2SIO 1SIO or 2SIO 1SIO Main clock, PLL clock, or PCLK1=1 on-chip oscillator clock 8SIO 32SIO (UART0) UART reception Clock source selection Receive 1/16 clock Reception CLK1 to CLK0 Clock synchronous control circuit Transmit/ type U0BRG 1SIO or 2SIO Internal receive...
Page 187 14. Serial I/O Clock synchronous type UART (7 bits) disabled UART (8 bits) Clock UARTi receive register synchronous UART (7 bits) type STPS=0 PRYE=0 RxDi STPS=1 UART PRYE=1 UART (9 bits) enabled Clock synchronous type UART (8 bits) UART (9 bits) UARTi receive buffer register Address 03A6...
Page 188 14.Serial I/O No reverse IOPOL=0 RxD data RxD2 reverse circuit IOPOL=1 Reverse Clock synchronous type UART (7 bits) disabled UART Clock UARTi receive register UART(7 bits) (8 bits) synchronous STPS=0 PRYE=0 type STPS=1 PRYE=1 Clock UART UART synchronous type enabled (9 bits) UART (8 bits)
Page 189 14. Serial I/O UARTi Transmit Buffer Register (i=0 to 2) Symbol Address After Reset (b15) (b8) U0TB 03A3 -03A2 Indeterminate U1TB 03AB -03AA Indeterminate U2TB 037B -037A Indeterminate Function Transmit data Nothing is assigned. When write, set to "0". When read, its content is indeterminate. NOTES: 1.
Page 190 14.Serial I/O UARTi Transmit/receive Mode Register (i=0, 1) Symbol Address After Reset U0MR, U1MR 03A0 , 03A8 Function Bit Name Symbol SMD0 b2 b1 b0 Serial I/O mode select bit 0 0 0 : Serial I/O disabled 0 0 1 : Clock synchronous serial I/O mode 1 0 0 : UART mode transfer data 7 bits long SMD1 1 0 1 : UART mode transfer data 8 bits long...
Page 191 14. Serial I/O UARTi Transmit/receive Control Rregister 0 (i=0 to 2) Symbol Address After Reset U0C0 to U2C0 03A4 , 03AC , 037C 00001000 Bit Name Function Symbol b1 b0 CLK0 BRG count source 0 0 : f or f is selected 1SIO 2SIO...
Page 192 14.Serial I/O UARTi Transmit/receive Control Register 1 (i=0, 1) Symbol Address After Reset U0C1, U1C1 03A5 ,03AD 00000010 Function Bit Name Symbol Transmit enable bit 0 : Transmission disabled 1 : Transmission enabled Transmit buffer 0 : Data present in UiTB register empty flag 1 : No data present in UiTB register Receive enable bit...
Page 193 14. Serial I/O UART2 Special Mode Register b7 b6 b5 b4 b3 b2 b1 b0 Symbol Address After Reset U2SMR 0377 X0000000 Function Bit Name Symbol 0 : Other than I C bus mode IICM C bus mode select bit 1 : I C bus mode Arbitration lost detecting...
Page 194 14.Serial I/O UART2 Special Mode Register 3 b7 b6 b5 b4 b3 b2 b1 b0 Symbol Address After Reset U2SMR3 0375 000X0X0X Bit Name Function Symbol Nothing is assigned. (b0) When write, set “0”. When read, its content is indeterminate. CKPH Clock phase set bit 0 : Without clock delay...
Page 195: Clock Synchronous Serial I/O Mode
14. Serial I/O 14.1.1 Clock Synchronous serial I/O Mode The clock synchronous serial I/O mode uses a transfer clock to transmit and receive data. Table 14.1 lists the specifications of the clock synchronous serial I/O mode. Table 14.2 lists the registers used in clock synchronous serial I/O mode and the register values set.
Page 196 14.Serial I/O Table 14.2 Registers to Be Used and Settings in Clock Synchronous Serial I/O Mode Register Function UiTB 0 to 7 Set transmission data UiRB 0 to 7 Reception data can be read Overrun error flag UiBRG 0 to 7 Set a transfer rate UiMR SMD2 to SMD0...
Page 197 14. Serial I/O Table 14.3 lists pin functions for the case where the multiple transfer clock output pin select function is deselected. Table 14.4 lists the P6 pin functions during clock synchronous serial I/O mode. Note that for a period from when the UARTi operation mode is selected to when transfer starts, the TxDi pin outputs an “H”.
Page 198 14.Serial I/O (1) Example of Transmit Timing (Internal clock is selected) Transfer clock “1” UiC1 register “0” Write data to the UiTB register TE bit “1” UiC1 register TI bit “0” Transferred from UiTB register to UARTi transmit register “H” CTSi “L”...
Page 199 14. Serial I/O 14.1.1.1 Counter Measure for Communication Error Occurs If a communication error occurs while transmitting or receiving in clock synchronous serial I/O mode, follow the procedures below. •Resetting the UiRB register (i=0 to 2) (1) Set the RE bit in the UiC1 register to “0” (reception disabled) (2) Set the SMD2 to SMD0 bits in the UiMR register to “000 ”...
Page 200 14.Serial I/O 14.1.1.2 CLK Polarity Select Function Use the CKPOL bit in the UiC0 register (i=0 to 2) to select the transfer clock polarity. Figure 14.11 shows the polarity of the transfer clock. (1) When the CKPOL bit in the UiC0 register is set to "0" (transmit data output at the falling edge and the receive data taken in at the rising edge of the transfer clock) (2) When the CKPOL bit in the UiC0 register is set to "1"...
Page 201 14. Serial I/O 14.1.1.4 Continuous receive mode When the UiRRM bit (i=0 to 2) is set to "1" (continuous receive mode), the TI bit in the UiC1 register is set to “0” (data present in the UiTB register) by reading the UiRB register. In this case, i.e., UiRRM bit is set to "1", do not write dummy data to the UiTB register in a program.
Page 202 14.Serial I/O _______ _______ 14.1.1.7 CTS/RTS separate function (UART0) _______ _______ _______ _______ This function separates CTS /RTS , outputs RTS from the P6 pin, and accepts as input the CTS from the P6 pin or P7 pin. To use this function, set the register bits as shown below. _______ _______ •...
Page 203: Clock Asynchronous Serial I/O (Uart) Mode
14. Serial I/O 14.1.2 Clock Asynchronous Serial I/O (UART) Mode The UART mode allows transmitting and receiving data after setting the desired transfer rate and transfer data format. Table 14.5 lists the specifications of the UART mode. Table 14.5 UART Mode Specifications Item Specification Transfer data format...
Page 204 14.Serial I/O Table 14.6 Registers to Be Used and Settings in UART Mode Register Function UiTB 0 to 8 Set transmission data UiRB 0 to 8 Reception data can be read OER,FER,PER,SUM Error flag UiBRG 0 to 7 Set a transfer rate UiMR SMD2 to SMD0 Set these bits to ‘100...
Page 205 14. Serial I/O Table 14.7 lists the functions of the input/output pins in UART mode. Table 14.8 lists the P6 pin func- tions during UART mode. Note that for a period from when the UARTi operation mode is selected to when transfer starts, the TxDi pin outputs an “H”.
Page 206 14.Serial I/O • Example of transmit timing when transfer data is 8-bit long (parity enabled, one stop bit) The transfer clock stops momentarily as CTSi is “H” when the stop bit is checked. The transfer clock starts as the transfer starts immediately CTSi changes to “L”. Transfer clock UiC1 register “1”...
Page 207 14. Serial I/O • Example of receive timing when transfer data is 8 bits long (parity disabled, one stop bit) UiBRG count source “1” UiC1 register RE bit “0” Stop bit Start RxDi Sampled “L” Receive data taken in Transfer clock Reception triggered when transfer clock Read out from Transferred from UARTi receive...
Page 208 14.Serial I/O 14.1.2.2 Counter Measure for Communication Error If a communication error occurs while transmitting or receiving in UART mode, follow the procedure below. • Resetting the UiRB register (i=0 to 2) (1) Set the RE bit in the UiC1 register to “0” (reception disabled) (2) Set the RE bit in the UiC1 register to “1”...
Page 209 14. Serial I/O 14.1.2.4 Serial Data Logic Switching Function (UART2) The data written to the U2TB register has its logic reversed before being transmitted. Similarly, the received data has its logic reversed when read from the U2RB register. Figure 14.19 shows serial data logic.
Page 210 14.Serial I/O _______ _______ 14.1.2.6 CTS/RTS Separate Function (UART0) _______ _______ _______ _______ This function separates CTS /RTS , outputs RTS from the P6 pin, and accepts as input the CTS from the P6 pin or P7 pin. To use this function, set the register bits as shown below. _______ _______ •...
Page 211: Special Mode 1 (I 2 C Bus Mode)(Uart2)
14. Serial I/O 14.1.3 Special Mode 1 (I C bus mode)(UART2) C bus mode is provided for use as a simplified I C interface compatible mode. Table 14.10 lists the specifications of the I C bus mode. Tables 14.11 and 14.12 list the registers used in the I C bus mode and the register values set.
Page 212 14. Serial I/O Start and stop condition generation block SDA2 DMA0, DMA1 request STSPSEL=1 (UART1: DMA0 only) Delay STSP circuit STSP STSPSEL=0 IICM2=1 Transmission UART2 transmit, register NACK interrupt ACKC=1 ACKC=0 request UART2 IICM=1 and IICM2=0 SDHI ACKD bit DMA0 Arbitration (UART0, UART2) Noise...
Page 213 14. Serial I/O Table 14.11 Registers to Be Used and Settings in I C bus mode (1) (Continued) Register Function Master Slave U2TB 0 to 7 Set transmission data Set transmission data U2RB 0 to 7 Reception data can be read Reception data can be read ACK or NACK is set in this bit ACK or NACK is set in this bit...
Page 214 14. Serial I/O Table 14.12 Registers to Be Used and Settings in I C bus Mode (2) (Continued) Register Function Master Slave U2SMR4 STAREQ Set this bit to “1” to generate start Set to “0” condition RSTAREQ Set this bit to “1” to generate restart Set to “0”...
Page 215 14. Serial I/O Table 14.13 I C bus Mode Functions C bus mode (SMD2 to SMD0 = 010 , IICM = 1) Clock synchronous serial I/O Function mode (SMD2 to SMD0 = 001 IICM2 = 0 IICM2 = 1 IICM = 0) (NACK/ACK interrupt) (UART transmit/ receive interrupt) CKPH = 0...
Page 216 14. Serial I/O (1) When the IICM2 bit is set to "0" (ACK or NACK interrupt) and the CKPH bit is set to "0" (No clock delay) SCL2 (ACK or NACK) SDA2 ACK interrupt (DMA request) or NACK interrupt Data is transferred to the U2RB register •••...
Page 217 14. Serial I/O 14.1.3.1 Detection of Start and Stop Condition Whether a start or a stop condition has been detected is determined. A start condition-detected interrupt request is generated when the SDA pin changes state from high to low while the SCL pin is in the high state.
Page 218 14. Serial I/O Table 14.14 STSPSEL Bit Functions Function STSPSEL = 0 STSPSEL = 1 Output of SCL2 and SDA2 pins Output transfer clock and data/ The STAREQ, RSTAREQ and Program with a port determines STPREQ bit determine how the how the start condition or stop start condition or stop condition is condition is output...
Page 219 14. Serial I/O 14.1.3.4 Transfer Clock Data is transmitted/received using a transfer clock like the one shown in Figure 14.25. The CSC bit in the U2SMR2 register is used to synchronize the internally generated clock (internal SCL2) and an external clock supplied to the SCL pin.
Page 220 14. Serial I/O 14.1.3.7 ACK and NACK If the STSPSEL bit in the U2SMR4 register is set to “0” (start and stop conditions not generated) and the ACKC bit in the U2SMR4 register is set to “1” (ACK data output), the value of the ACKD bit in the U2SMR4 register is output from the SDA pin.
Page 221: Special Mode 2 (Uart2)
14. Serial I/O 14.1.4 Special Mode 2 (UART2) Multiple slaves can be serially communicated from one master. Transfer clock polarity and phase are selectable. Table 14.15 lists the specifications of Special Mode 2. Table 14.16 lists the registers used in Special Mode 2 and the register values set.
Page 222 14. Serial I/O Microcomputer Microcomputer (Master) (Slave) Microcomputer (Slave) Figure 14.26 Serial Bus Communication Control Example (UART2) Table 14.16 Registers to Be Used and Settings in Special Mode 2 Register Function U2TB 0 to 7 Set transmission data U2RB 0 to 7 Reception data can be read Overrun error flag U2BRG...
Page 223 14. Serial I/O 14.1.4.1 Clock Phase Setting Function One of four combinations of transfer clock phases and polarities can be selected using the CKPH bit in the U2SMR3 register and the CKPOL bit in the U2C0 register. Make sure the transfer clock polarity and phase are the same for the master and slave to communi- cate.
Page 224 14. Serial I/O "H" Slave control input "L" "H" Clock input "L" (CKPOL=0, CKPH=0) Clock input "H" (CKPOL=1, CKPH=0) "L" "H" Data output timing "L" Data input timing Indeterminate Figure 14.28 Transmission and Reception Timing (CKPH="0") in Slave Mode (External Clock) "H"...
Page 225: Special Mode 3 (Iebus Mode)(Uart2)
14. Serial I/O 14.1.5 Special Mode 3 (IEBus mode)(UART2) In this mode, one bit in the IEBus is approximated with one byte of UART mode waveform. Table 14.17 lists the registers used in IEBus mode and the register values set. Figure 14.30 shows the functions of bus collision detect function related bits.
Page 226 14. Serial I/O (1) The ABSCS bit in the U2SMR register (bus collision detect sampling clock select) If ABSCS=0, bus collision is determined at the rising edge of the transfer clock Transfer clock TxD2 RxD2 Input to TA0 Timer A0 If ABSCS is set to "1", bus collision is determined when timer A0 (one-shot timer mode) underflows (2) The ACSE bit in the U2SMR register (auto clear of transmit enable bit)
Page 227: Special Mode 4 (Sim Mode) (Uart2)
14. Serial I/O 14.1.6 Special Mode 4 (SIM Mode) (UART2) Based on UART mode, this is an SIM interface compatible mode. Direct and inverse formats can be implemented, and this mode allows output of a low from the TxD2 pin when a parity error is detected. Table 14.18 lists the specifications of SIM mode.
Page 228 14. Serial I/O Table 14.19 Registers to Be Used and Settings in SIM Mode Register Function U2TB 0 to 7 Set transmission data U2RB 0 to 7 Reception data can be read OER,FER,PER,SUM Error flag U2BRG 0 to 7 Set a transfer rate U2MR SMD2 to SMD0 Set to "101...
Page 229 14. Serial I/O (1) Transmit Timing Transfer Clock "1" TE bit in U2C1 Data is written to register "0" the UARTi register TI bit in U2C1 "1" register "0" Data is transferred from the U2TB register to the UART2 transmit Stop Parity register...
Page 230 14. Serial I/O Figure 14.32 shows the example of connecting the SIM interface. Connect T and R and apply pull-up. Microcomputer SIM card Figure 14.32 SIM Interface Connection 14.1.6.1 Parity Error Signal Output The parity error signal is enabled by setting the U2ERE bit in theU2C1 register to “1”. •...
Page 231 14. Serial I/O 14.1.6.2 Format • Direct Format Set the PRY bit in the U2MR register to “1”, the UFORM bit in U2C0 register to “0” and the U2LCH bit in U2C1 register to “0”. • Inverse Format Set the PRY bit to “0”, UFORM bit to “1” and U2LCH bit to “1”. Figure 14.34 shows the SIM interface format.
Page 232: Si/O3 And Si/O4
14. Serial I/O 14.2 SI/O3 and SI/O4 Note The SI/O4 interrupt of peripheral function interrupt is not available in the 64-pin package. SI/O3 and SI/O4 are exclusive clock-synchronous serial I/Os. Figure 14.35 shows the block diagram of SI/O3 and SI/O4, and Figure 14.36 shows the SI/O3 and SI/O4- related registers.
Page 233 14. Serial I/O ( 1 ) S I / O i c o n t r o l R e g i s t e r ( i = 3 , 4 ) S y m b o l A d d r e s s A f t e r R e s e t S 3 C 0 3 6 2...
Page 234 14. Serial I/O Table 14.20 SI/O3 and SI/O4 Specifications Item Specification Transfer data format • Transfer data length: 8 bits Transfer clock • The SMi6 bit in the SiC (i=3, 4) register is set to “1” (internal clock) : fj/ (2(n+1)) fj = f .
Page 235: Si/Oi Operation Timing
14. Serial I/O 14.2.1 SI/Oi Operation Timing Figure 14.37 shows the SI/Oi operation timing 1.5 cycle (max) "H" SI/Oi internal clock "L" "H" CLKi output "L" Signal written to the "H" SiTRR register "L" i output "H" "L" "H" i input "L"...
Page 236: Functions For Setting An Souti Initial Value
14. Serial I/O 14.2.3 Functions for Setting an S i Initial Value If the SMi6 bit in SiC register is set to 0 (external clock), the S pin output level can be fixed high or low OUTi when not transferring data. However, when transmitting data consecutively, the last bit (bit 0) value of the last transmitted data is retained between the sccessive data transmissions.
Page 237: A/D Converter
15. A/D Converter 15. A/D Converter Note Ports P0 to P0 (AN0 to AN0 ), P1 to P1 (AN2 to AN2 ) and P9 to P9 (AN2 to AN2 ) are not available in M16C/28 (64-pin package). Do not use port P0 to P0 (AN0 to AN0...
Page 238 15. A/D Converter A/D conversion rate selection CKS1=1 CKS2=0 ø CKS0=1 CKS1=0 CKS0=0 CKS2=1 Resistor ladder VCUT=0 VCUT=1 Successive conversion register ADCON1 register (address 03D7 ADCON0 register (address 03D6 Addresses A/D register 0(16) (03C1 to 03C0 (03C3 to 03C2 A/D register 1(16) (03C5 to 03C4 A/D register 2(16)
Page 239 15. A/D Converter A/D Control Register 0 Symbol Address After Reset ADCON0 03D6 00000XXX Bit Symbol Bit Name Function Analog Input Pin Select Function varies with each operation mode b4 b3 A/D Operation Mode 0 0 : One-shot mode or Delayed trigger mode 0,1 Select Bit 0 0 1 : Repeat mode 1 0 : Single sweep mode or...
Page 240 15. A/D Converter A/D Trigger Control Register (1, 2) Symbol Address After Reset ADTRGCON 03D2 Bit Symbol Bit Name Function 0 : Other than simultaneous sample sweep A/D Operation Mode mode or delayed trigger mode 0,1 Select Bit 2 1 : Simultaneous sample sweep mode or delayed trigger mode 0,1 0 : Other than delayed trigger mode 0,1 A/D Operation Mode...
Page 241 15. A/D Converter A/D Conversion Status Register 0 Symbol Address After reset ADSTAT0 03D3 Bit Symbol Bit Name Function AN1 Trigger Status Flag 0 : AN1 trigger did not occur during ADERR0 AN0 conversion 1 : AN1 trigger occured during AN0 conversion ADERR1 Conversion Termination...
Page 242 15. A/D Converter Timer B2 Special Mode Register Symbol Address After Reset TB2SC 039E X0000000 Bit Symbol Bit Name Function Timer B2 reload timing 0 : Timer B2 underflow PWCOM switch bit 1 : Timer A output at odd-numbered 0 : Three-phase output forcible cutoff by SD pin input (high impedance) Three-phase output port disabled...
Page 243: Operating Modes
15. A/D Converter 15.1 Operating Modes 15.1.1 One-Shot Mode In one-shot mode, analog voltage applied to a selected pin is once converted to a digital code. Table 15.3 shows the one-shot mode specifications. Figure 15.6 shows the operation example in one-shot mode. Figure 15.7 shows the ADCON0 to ADCON2 registers in one-shot mode.
Page 244 15. A/D Converter A/D Control Register 0 Symbol Address After Reset ADCON0 03D6 00000XXX Bit Symbol Bit Name Function b2 b1 b0 Analog Input Pin 0 0 0 : Select AN (2, 3) Select Bit 0 0 1 : Select AN 0 1 0 : Select AN 0 1 1 : Select AN 1 0 0 : Select AN...
Page 245: Repeat Mode
15. A/D Converter 15.1.2 Repeat mode In repeat mode, analog voltage applied to a selected pin is repeatedly converted to a digital code. Table 15.4 shows the repeat mode specifications. Figure 15.8 shows the operation example in repeat mode. Figure 15.9 shows the ADCON0 to ADCON2 registers in repeat mode. Table 15.4 Repeat Mode Specifications Item Specification...
Page 246 15. A/D Converter A/D Control Register 0 Symbol Address After Reset ADCON0 03D6 00000XXX Bit Symbol Bit Name Function b2 b1 b0 Analog Input Pin 0 0 0 : Select AN (2, 3) Select Bit 0 0 1 : Select AN 0 1 0 : Select AN 0 1 1 : Select AN 1 0 0 : Select AN...
Page 247: Single Sweep Mode
15. A/D Converter 15.1.3 Single Sweep Mode In single sweep mode, analog voltages applied to the selected pins are converted one-by-one to a digital code. Table 15.5 shows the single sweep mode specifications. Figure 15.10 shows the operation ex- ample in single sweep mode. Figure 15.11 shows the ADCON0 to ADCON2 registers in single sweep mode.
Page 248 15. A/D Converter A/D Control Register 0 Symbol Address After Reset ADCON0 03D6 00000XXX Bit Symbol Bit Name Function Analog Input Pin Invalid in single sweep mode Select Bit b4 b3 A/D Operation Mode 1 0 : Single sweep mode or simultaneous Select Bit 0 sample sweep mode Trigger Select Bit...
Page 249: Repeat Sweep Mode 0
15. A/D Converter 15.1.4 Repeat Sweep Mode 0 In repeat sweep mode 0, analog voltages applied to the selected pins are repeatedly converted to a digital code. Table 15.6 shows the repeat sweep mode 0 specifications. Figure 15.12 shows the opera- tion example in repeat sweep mode 0.
Page 250 15. A/D Converter A/D Control Register 0 Symbol Address After Reset ADCON0 03D6 00000XXX Bit Symbol Bit Name Function Analog Input Pin Invalid in repeat sweep mode 0 Select Bit b4 b3 A/D Operation Mode 1 1 : Repeat sweep mode 0 or Select Bit 0 Repeat sweep mode 1 0 : Software trigger...
Page 251: Repeat Sweep Mode 1
15. A/D Converter 15.1.5 Repeat Sweep Mode 1 In repeat sweep mode 1, analog voltage is applied to the all selected pins are converted to a digital code, with mainly used in the selected pins. Table 15.7 shows the repeat sweep mode 1 specifications. Figure 15.14 shows the operation example in repeat sweep mode 1.
Page 252 15. A/D Converter A/D Control Register 0 Symbol Address After Reset ADCON0 03D6 00000XXX Bit Symbol Bit Name Function Analog Input Pin Invalid in repeat sweep mode 1 Select Bit b4 b3 A/D Operation Mode 1 1 : Repeat sweep mode 0 or Select Bit 0 Repeat sweep mode 1 0 : Software trigger...
Page 253: Simultaneous Sample Sweep Mode
15. A/D Converter 15.1.6 Simultaneous Sample Sweep Mode In simultaneous sample sweep mode, analog voltages applied to the selected pins are converted one-by- one to a digital code. The input voltages of AN0 and AN1 are sampled simultaneously using two circuits of sample and hold circuit.
Page 254 15. A/D Converter A/D Control Register 0 Symbol Address After Reset ADCON0 03D6 00000XXX Bit Symbol Bit Name Function Analog Input Pin Invalid in simultaneous sample sweep mode Select Bit b4 b3 A/D Operation Mode 1 0 : Single sweep mode or simultaneous Select Bit 0 sample sweep mode Refer to Table 15.9...
Page 255 15. A/D Converter A/D Trigger Control Register Symbol Address After Reset ADTRGCON 03D2 Bit Symbol Bit Name Function 1 : Simultaneous sample sweep mode A/D Operation Mode or delayed trigger mode 0, 1 Select Bit 2 0 : Any mode other than delayed trigger A/D Operation Mode mode 0,1 Select Bit 3...
Page 256: Delayed Trigger Mode 0
15. A/D Converter 15.1.7 Delayed Trigger Mode 0 In delayed trigger mode 0, analog voltages applied to the selected pins are converted one-by-one to a digital code. The delayed trigger mode 0 used in combination with A/D trigger mode of Timer B. The Timer B0 underflow starts a single sweep conversion.
Page 257 15. A/D Converter •Example when selecting AN to AN to A/D sweep pins (SCAN1 to SCAN0="01 ") •Example 1: When Timer B1 underflow is generated during AN pin conversion A/D pin input voltage sampling Timer B0 underflow A/D pin conversion Timer B1 underflow •Example 2: When Timer B1 underflow is generated after AN pin conversion...
Page 258 15. A/D Converter •Example when selecting AN to AN to A/D sweep pins (SCAN1 to SCAN0="01 ") •Example 1: When Timer B1 underflow is generated during AN pin conversion A/D pin input voltage sampling Timer B0 underflow A/D pin conversion Timer B1 underflow "1"...
Page 259 15. A/D Converter •Example 3: When Timer B0 underflow is generated during A/D pin conversion of any pins except AN Timer B0 underflow A/D pin input Timer B0 underflow (Abort othrt pins conversion ) voltage sampling Timer B1 underflow Timer B1 underflow A/D pin conversion "1"...
Page 260 15. A/D Converter A/D Control Register 0 Symbol Address After Reset ADCON0 03D6 00000XXX Bit Symbol Bit Name Function b2 b1 b0 Analog Input Pin 1 1 1 : Set to "111b" in delayed trigger Select Bit mode 0 b4 b3 A/D Operation Mode 0 0 : One-shot mode or delayed trigger mode Select Bit 0...
Page 261 15. A/D Converter A/D Trigger Control Register Symbol Address After Reset ADTRGCON 03D2 Bit Symbol Bit Name Function Simultaneous sample sweep mode or A/D Operation Mode delayed trigger mode 0,1 Select Bit 2 Delayed trigger mode 0, 1 A/D Operation Mode Select Bit 3 Refer to Table 15.11 AN0 Trigger Select Bit...
Page 262: Delayed Trigger Mode 1
15. A/D Converter 15.1.8 Delayed Trigger Mode 1 In delayed trigger mode 1, analog voltages applied to the selected pins are converted one-by-one to a ___________ digital code. When the input of the AD pin (falling edge) changes state from “H” to “L”, a single sweep conversion is started.
Page 263 15. A/D Converter •Example when selecting AN to AN to A/D sweep pins (SCAN1 to SCAN0="01 ") •Example 1: When AD pin falling edge is generated during AN pin conversion A/D pin input voltage sampling A/D pin conversion pin input •Example 2: When AD pin falling edge is generated again after AN pin conversion...
Page 264 15. A/D Converter • E x a m p l e w h e n s e l e c t i n g A N t o A N t o A / D s w e e p p i n s ( S C A N 1 t o S C A N 0 = " 0 1 ") •...
Page 265 15. A/D Converter •Example 3: When AD input falling edge is generated more than two times after AN pin conversion A/D pin input voltage sampling A/D pin conversion pin input (valid after single sweep conversion) (invalid) ADST flag "1" "0" Do not set to "1"...
Page 266 15. A/D Converter A/D Control Register 0 Symbol Address After Reset ADCON0 03D6 00000XXX Bit Symbol Bit Name Function b2 b1 b0 Analog Input Pin 1 1 1 : Set to "111b" in delayed trigger Select Bit mode 1 b4 b3 A/D Operation Mode 0 0 : One-shot mode or delayed trigger mode Select Bit 0...
Page 267 15. A/D Converter A/D Trigger Control Register Symbol Address After Reset ADTRGCON 03D2 Bit Symbol Bit Name Function Simultaneous sample sweep mode or A/D Operation Mode delayed trigger mode 0,1 Select Bit 2 Delayed trigger mode 0, 1 A/D Operation Mode Select Bit 3 Refer to Table 15.13 AN0 Trigger Select Bit...
Page 268: Resolution Select Function
15. A/D Converter 15.2 Resolution Select Function The BITS bit in the ADCON1 register determines the resolution. When the BITS bit is set to “1” (10-bit precision), the A/D conversion result is stored into bits 0 to 9 in the ADi register (i=0 to 7). When the BITS bit is set to “0”...
Page 269: Output Impedance Of Sensor Under A/D Conversion
15. A/D Converter 15.5 Output Impedance of Sensor under A/D Conversion To carry out A/D conversion properly, charging the internal capacitor C shown in Figure 15.29 has to be completed within a specified period of time. T (sampling time) as the specified time. Let output imped- ance of sensor equivalent circuit be R0, microcomputer’s internal resistance be R, precision (error) of the A/D converter be X, and the A/D converter’s resolution be Y (Y is 1024 in the 10-bit mode, and 256 in the 8-bit mode).
Page 270: Multi-Master I C Bus Interface
16. MULTI-MASTER I C bus INTERFACE 16. Multi-master I C bus Interface The multi-master I C bus interface is a serial communication circuit based on Philips I C bus data transfer format, equipped with arbitration lost detection and synchronous functions. Figure 16.1 shows a block diagram of the multi-master I C bus interface and Table 16.1 lists the multi-master I C bus interface func-...
Page 271: Multi-Master I 2 C Bus Interface
16. MULTI-MASTER I C bus INTERFACE Figure 16.1 Block Diagram of Multi-Master I C bus Interface page 251...
Page 272 16. MULTI-MASTER I C bus INTERFACE C0 Address Register Symbol Address After Reset S0D0 02E2 Bit Symbol Bit Name Function Reserved bit Set to “0” (b0) Compare with received SAD0 Slave address address data SAD1 SAD2 SAD3 SAD4 SAD5 SAD6 Figure 16.2 S0D0 Register page 252...
Page 273 16. MULTI-MASTER I C bus INTERFACE I C 0 D a t a S h i f t R e g i s t e r Symbol Address After Reset 02E0 Function Transmit/receive data are stored. In master transmit mode, the start condition/stop condition are triggered by writing data to the register (refer to 16.9 START Condition Generation Method and 16.11 STOP Condition Generation Method).
Page 274 16. MULTI-MASTER I C bus INTERFACE C0 Control Register 0 Symbol Address After Reset S1D0 02E3 Bit Symbol Bit Name Function Bit counter b2 b1 b0 0 : 8 (Number of transmit/receive 1 : 7 bits) 0 : 6 1 : 5 0 : 4 1 : 3 0 : 2...
Page 275 16. MULTI-MASTER I C bus INTERFACE C0 Status Register Symbol Address After Reset 02E8 0001000X Bit Symbol Bit Name Function Last Receive Bit 0: Last bit = 0 1: Last bit = 1 0: No general call detected ADR0 General Call Detecting Flag 1: General call detected Slave Address Comparison Flag 0: No address matched...
Page 276 16. MULTI-MASTER I C bus INTERFACE C0 Control Register 1 Symbol Address After Reset S3D0 02E6 00110000 Bit Symbol Bit Name Function The Interrupt Enable Bit for 0: Disable the I C bus interface STOP Condition Detection interrupt of STOP condition detection 1: Enable the I C bus interface...
Page 277 16. MULTI-MASTER I C bus INTERFACE C0 Control Register 2 Symbol Address After Reset S4D0 02E7 Bit Symbol Bit Name Function 0 : Disabled Time Out Detection 1 : Enabled Function Enable Bit 0 : Not detected Time Out Detection Flag 1 : Detected TOSEL Time Out Detection Time...
Page 278 16. MULTI-MASTER I C bus INTERFACE C0 Start/stop Condition Control Register Symbol Address After Reset S2D0 02E5 00011010 Bit Symbol Bit Name Function SSC0 START/STOP Condition Setting for detection condition Setting Bits of START/STOP condition. See Table 16.2. SSC1 SSC2 SSC3 SSC4 0: Active in falling edge...
Page 279: I 2 C0 Data Shift Register (S00 Register)
16. MULTI-MASTER I C bus INTERFACE 16.1 I C0 Data Shift Register (S00 register) The S00 register is an 8-bit data shift register to store a received data and to write a transmit data. When a transmit data is written to the S00 register, the transmit data is synchronized with a SCL clock and the data is transferred from bit 7.
Page 280: I 2 C0 Clock Control Register (S20 Register)
16. MULTI-MASTER I C bus INTERFACE 16.3 I C0 Clock Control Register (S20 register) The S20 register is used to set theACK control, SCL mode and the SCL frequency. 16.3.1 Bits 0 to 4: SCL Frequency Control Bits (CCR0–CCR4) These bits control the SCL frequency. See Table 16.3 . 16.3.2 Bit 5: SCL Mode Specification Bit (FAST MODE) The FAST MODE bit selects SCL mode.
Page 281 16. MULTI-MASTER I C bus INTERFACE Table 16.3 Setting values of S20 register and SCL frequency Setting value of CCR4 to CCR0 SCL frequency (at V =4MHz, unit : kHz) CCR4 CCR3 CCR2 CCR1 CCR0 Standard clock mode High-speed clock mode Setting disabled Setting disabled Setting disabled...
Page 282: I 2 C0 Control Register 0 (S1D0)
16. MULTI-MASTER I C bus INTERFACE 16.4 I C0 Control Register 0 (S1D0) The S1D0 register controls data communication format. 16.4.1 Bits 0 to 2: Bit Counter (BC0–BC2) The BC2 to BC0 bits decide how many bits are in one byte data transferred next. After the selected numbers of bits are transferred successfully, I C bus interface interrupt request is gnerated and the BC2 to BC0 bits are reset to "000...
Page 283: Bit 7: I C Bus Interface Pin Input Level Select Bit (Tiss)
16. MULTI-MASTER I C bus INTERFACE 16.4.5 Bit 7: I C bus Interface Pin Input Level Select Bit (TISS) The TISS bit selects the input level of the SCL and SDA pins for the multi-master I C bus interface. When the TISS bit is set to “1”, the P2 and P2 become the SMBus input level.
Page 284: I 2 C0 Status Register (S10 Register)
16. MULTI-MASTER I C bus INTERFACE 16.5 I C0 Status Register (S10 register) The S10 register monitors the I C bus interface status. When using the S10 register to check the status, use the 6 low-order bits for read only. 16.5.1 Bit 0: Last Receive Bit (LRB) The LRB bit stores the last bit value of received data.
Page 285: Bit 4: I C Bus Interface Interrupt Request Bit (Pin)
16. MULTI-MASTER I C bus INTERFACE 16.5.5 Bit 4: I C bus Interface Interrupt Request Bit (PIN) The PIN bit generates an I C bus interface interrupt request signal. Every one byte data is ransferred, the PIN bit is changed from “1” to “0”. At the same time, an I C bus interface interrupt request is generated.
Page 286: Bit 6: Communication Mode Select Bit (Transfer Direction Select Bit: Trx)
16. MULTI-MASTER I C bus INTERFACE 16.5.7 Bit 6: Communication Mode Select Bit (Transfer Direction Select Bit: TRX) This TRX bit decides a transfer direction for data communication. When the TRX bit is set to “0”, receive mode is entered and data is received from a transmit device. When the TRX bit is set to “1”, transmit mode is entered, and address data and control data are output to the SDA synchronized with a clock generated in the SCL...
Page 287: I 2 C0 Control Register 1 (S3D0 Register)
16. MULTI-MASTER I C bus INTERFACE 16.6 I C0 Control Register 1 (S3D0 register) The S3D0 register controls the I C bus interface circuit. 16.6.1 Bit 0 : Interrupt Enable Bit by STOP Condition (SIM ) The SIM bit enables the I C bus interface interrupt request by detecting a STOP condition.
Page 288: Bits 2,3 : Port Function Select Bits Ped, Pec
16. MULTI-MASTER I C bus INTERFACE In receive mode, ACK bit = 1 WIT bit = 0 7 clock 8 clock 1 clock clock 7 bit 8 bit ACK bit 1 bit ACK-BIT bit PIN flag Internal WAIT flag C bus interface interrupt request signal The writing signal of the S00 register...
Page 289: Bits 4,5 : Sda/Scl Logic Output Value Monitor Bits Sdam/Sclm
16. MULTI-MASTER I C bus INTERFACE 16.6.4 Bits 4,5 : SDA/SCL Logic Output Value Monitor Bits SDAM/SCLM The SDAM/SCLM bits can monitor the logic value of the SDA and SCL output signals from the I C bus interface circuit. The SDAM bit monitors the SDA output logic value. The SCLM bit monitors the SCL output logic value.
Page 290: I 2 C0 Control Register 2 (S4D0 Register)
16. MULTI-MASTER I C bus INTERFACE 16.7 I C0 Control Register 2 (S4D0 Register) The S4D0 register controls the error communication detection. If the SCL clock is stopped counting dring data transfer, each device is stopped, staying online. To avoid the situation, the I C bus interface circuit has a function to detect the time-out when the SCL clock is stopped in high-level ("H") state for a specific period, and to generate an I...
Page 291: Bit0: Time-Out Detection Function Enable Bit (Toe)
16. MULTI-MASTER I C bus INTERFACE 16.7.1 Bit0: Time-Out Detection Function Enable Bit (TOE) The TOE bit enables the time-out detection function. When the TOE bit is set to "1", time-out is detected and the I C bus interface interrupt request is generated when the following conditions are met. 1) the BB flag in the S10 register is set to "1"...
Page 292: I 2 C0 Start/Stop Condition Control Register (S2D0 Register)
16. MULTI-MASTER I C bus INTERFACE 16.8 I C0 START/STOP Condition Control Register (S2D0 Register) The S2D0 register controls the START/STOP condition detections. 16.8.1 Bit0-Bit4: START/STOP Condition Setting Bits (SSC0-SSC4) The SCL release time and the set-up and hold times are mesured on the base of the I C bus system clock ).
Page 293: Start Condition Generation Method
16. MULTI-MASTER I C bus INTERFACE 16.9 START Condition Generation Method Set the MST bit, TRX bit and BB flags in the S10 register to "1" and set the PIN bit and 4 low-order bits in the S10 register to "0" simultaneously, to enter START condition standby mode, when the ES0 bit in the S1D0 register is set to “1”...
Page 294: Start Condition Duplicate Protect Function
16. MULTI-MASTER I C bus INTERFACE 16.10 START Condition Duplicate Protect Function A START condition is generated when verifying that the BB flag in the S10 register does not use buses. However, if the BB flag is set to "1" (bus busy) by the START condition which other master device gener- ates immediately after the BB flag is verified, the START condition is suspended by the START condition duplicate protect function.
Page 295 16. MULTI-MASTER I C bus INTERFACE C0 data shift register write signal Setup Hold time time Figure 16.16 Start condition generation timing diagram C0 data shift register write signal Hold Setup time time Figure 16.17 Stop condition generation timing diagram Table 16.8 Start/Stop generation timing table µ...
Page 296: Start/Stop Condition Detect Operation
16. MULTI-MASTER I C bus INTERFACE 16.12 START/STOP Condition Detect Operation Figure 16.18, Figure 16.19 and Table 16.10 show START/STOP condition detect operations. The SSC4 to SSC0 bits in the S2D0 register set the START/STOP conditions. The START/STOP condition can be detected only when the input signal of the SCL and SDA met the following conditions: the SCL...
Page 297: Address Data Communication
16. MULTI-MASTER I C bus INTERFACE 16.13 Address Data Communication This section describes data transmit control when a master transferes data or a slave receives data in 7-bit address format. Figure 16.20 (1) shows a master transmit format. (1) A master transmit device transmits data to a receive device Data Data Slave address...
Page 298: Example Of Slave Receive
16. MULTI-MASTER I C bus INTERFACE 16.13.2 Example of Slave Receive For example, a slave receives data as shown below when following conditions are met: high-speed clock mode, SCL frequency of 400 kHz, ACK clock added and addressing format. 1) Set a slave address in the 7 high-order bits in the S0D0 register 2) Set "A5 "...
Page 299: Precautions
16. MULTI-MASTER I C bus INTERFACE 16.14 Precautions (1) Access to the registers of I C bus interface circuit The following is precautions when read or write the control registers of I C bus interface circuit •S00 register Do not rewrite the S00 register during data transfer. If the bits in the S00 register are rewritten, the bit counter for transfer is reset and data may not be transferred successfully.
Page 300 16. MULTI-MASTER I C bus INTERFACE BB flag Bit reset signal Related bits 1.5V cycle Figure 16.21 The bit reset timing (The STOP condition detection) BB flag Bit reset signal Related bits BC0 - BC2 TRX(slave mode) Figure 16.22 The bit reset timing (The START condition detection) PIN bit BC0 - BC2 The bits referring...
Page 301 16. MULTI-MASTER I C bus INTERFACE (2) Generation of RESTART condition In order to generate a RESTART condition after 1-byte data transfer, write “E0 ” to the S10 register, enter START condition standby mode and leave the SDA open. Generate a START condition trigger by setting the S00 register after inserting a sufficient software wait until the SDA outputs a high-level ("H") signal.
Page 302: Programmable I/O Ports
17. Programmable I/O Ports 17. Programmable I/O Ports Note Ports P0 to P0 , P1 to P1 , P3 to P3 and P9 to P9 are not available in M16C/28 (64-pin package). The programmable input/output ports (hereafter referred to simply as “I/O ports”) consist of 71 lines P0, P1,P2, P3, P6, P7, P8, P9, P10 (except P9 ) for the 80-pin package, or 55 lines P0 to P0...
Page 303: Pin Assignment Control Register (Pacr)
17. Programmable I/O Ports 17.5 Pin Assignment Control Register (PACR) Figure 17.10 shows the PACR register. After reset, set bits PACR2 to PACR0 in the PACR register before a signal is input or output to each pin. When bits PACR2 to PACR0 are not set, some pins do not function as I/O ports.
Page 304 17. Programmable I/O Ports Pull-up selection Direction register to P0 , P9 (inside dotted-line to P10 included) Port latch Data bus to P3 (inside dotted-line not included) Analog input Pull-up selection Direction register to P1 (inside dotted-line included) Port P1 control register Port latch Data bus (inside dotted-line not included)
Page 305 17. Programmable I/O Ports Pull-up selection Direction register , P2 , P7 "1" , P7 Output Data bus Port latch Switching between CMOS and Input to respective peripheral functions Pull-up selection to P8 Direction register Port latch Data bus Input to respective peripheral functions Pull-up selection Direction register , P6...
Page 306 17. Programmable I/O Ports Pull-up selection Direction register , P6 “1” Output Port latch Data bus Switching between CMOS and Nch Pull-up selection NMI Enable Direction register Data bus Port latch Digital Debounce NMI Interrupt Input NMI Enable Pull-up selection Direction register , P10 to P10...
Page 307 17. Programmable I/O Ports Pull-up selection (inside dotted-line not included) Direction register “1” (inside dotted-line included) Output Port latch Data bus Analog input Input to respective peripheral functions Pull-up selection Direction register Data bus Port latch Pull-up selection Direction register Data bus Port latch NOTES:...
Page 308 17. Programmable I/O Ports signal input RESET RESET signal input Note 1: symbolizes a parasitic diode. Make sure the input voltage on each port will not exceed Vcc. Figure 17.5 I/O Pins page 288...
Page 309 17. Programmable I/O Ports Port Pi Direction Register (i=0 to 3, 6 to 8, and 10) Symbol Address After Reset PD0 to PD3 03E2 , 03E3 , 03E6 , 03E7 PD6 to PD8 03EE , 03EF , 03F2 PD10 03F6 Bit Symbol Bit Name Function...
Page 310 17. Programmable I/O Ports Port Pi Register (i=0 to 3, 6 to 8 and 10) Symbol Address After Reset P0 to P3 03E0 , 03E1 , 03E4 , 03E5 Indeterminate P6 to P8 03EC , 03ED , 03F0 Indeterminate 03F4 Indeterminate Bit Symbol Bit Name...
Page 311 17. Programmable I/O Ports Pull-up Control Register 0 (1) Symbol Address After Reset PUR0 03FC Bit Symbol Bit Name Function PU00 to P0 pull-up 0 : Not pulled up PU01 to P0 pull-up 1 : Pulled up PU02 to P1 pull-up PU03 to P1...
Page 312: Port Control Register
17. Programmable I/O Ports Port Control Register Symbpl Address After Reset 03FF Bit Symbol Bit Name Function PCR0 Port P1 control bit Operation performed when the P1 register is read 0: When the port is set for input, the input levels of P1 to P1 pins are read.
Page 313 17. Programmable I/O Ports NMI Digital Debounce Register (1,2) Symbol Address After Reset NDDR 033E Function Setting Range If the set value =n, - n = 0 to FE ; a signal with pulse width, greater than to FF (n+1)/f8, is input into NMI / SD - n = FF ;...
Page 314 17. Programmable I/O Ports Example of INT5 Digital Debounce Function (if P17DDR = "03 ") • Digital Debounce Filter Clock Port In Signal Out To INT5 Data Bus Reload Value Count Value Data Bus (write) (read) Reload Value Port In Signal Out Count Value Reload Value...
Page 315 17. Programmable I/O Ports Table 17.1 Unassigned Pin Handling in Single-Chip Mode t s i l l u t s i l l u NOTES: 1. If the port enters output mode and is left open, it is in input mode before output mode is entered by program after reset.
Page 316: Flash Memory Version
18. Flash Memory Version 18. Flash Memory Version 18.1 Flash Memory Performance In the flash memory version, rewrite operation to the flash memory can be performed in three modes : CPU rewrite mode, standard serial I/O mode and parallel I/O mode. Table 18.1 lists specifications of the flash memory version.
Page 317: Boot Mode
18. Flash Memory Version Table 18.2 Flash Memory Rewrite Modes Overview Flash Memory CPU Rewrite Mode Standard Serial I/O Mode Parallel I/O Mode Rewrite Mode Function Software command execu- A dedicated serial programer A dedicated parallel pro- tion by CPU rewrites the user rewrites the user ROM area.
Page 318: Memory Map
18. Flash Memory Version 18.2 Memory Map The flash memory contains the user ROM area and the boot ROM area (reserved area). Figures 18.1 to 18.4 show a block diagram of the flash memory. The user ROM area has space to store the microcomputer operation program in single-chip mode and two 2-Kbyte spaces: the block A and B.
Page 319 18. Flash Memory Version (Data space) 00F000 Block B :2K bytes 00F7FF 00F800 Block A :2K bytes 00FFFF (Program space) 0F0000 NOTES: Block 3 : 32K bytes 1. To specify a block, use the maximum even address in the block. 2.
Page 320 18. Flash Memory Version (Data space) 00F000 Block B :2K bytes 00F7FF 00F800 Block A :2K bytes 00FFFF (Program space) 0E8000 Block 4 : 32K bytes 0EFFFF 0F0000 Block 3 : 32K bytes NOTES: 1. To specify a block, use the maximum even address in the block. 2.
Page 321 18. Flash Memory Version (Data space) 00F000 Block B :2K bytes 00F7FF 00F800 Block A :2K bytes 00FFFF (Program space) 0E0000 Block 5 : 32K bytes 0E7FFF 0E8000 Block 4 : 32K bytes 0EFFFF 0F0000 Block 3 : 32K bytes NOTES: 1.
Page 322: Functions To Prevent Flash Memory From Rewriting
18. Flash Memory Version 18.3 Functions To Prevent Flash Memory from Rewriting The flash memory has a built-in ROM code protect function for parallel I/O mode and a built-in ID code check function for standard input/output mode to prevent the flash memory from reading or rewriting. 18.3.1 ROM Code Protect Function The ROM code protect function disables reading or changing the contents of the on-chip flash memory in parallel I/O mode.
Page 323 18. Flash Memory Version ROM Code Protect Control Address Symbol Address Factory Setting ROMCP 0FFFFF Bit Name Function Bit Symbol Reserved Bit Set to “1” (b5-b0) b7 b6 ROM Code Protect Level ROMCP1 1 Set Bit (1, 2, 3, 4) Enables protect 11: Disables protect NOTES:...
Page 324: Cpu Rewrite Mode
18. Flash Memory Version 18.4 CPU Rewrite Mode In CPU rewrite mode, the user ROM area can be rewritten when the CPU executes software commands. The user ROM area can be rewritten with microcomputer mounted on a board without using the ROM writer.
Page 325: Ew Mode 0
18. Flash Memory Version 18.4.1 EW Mode 0 The microcomputer enters CPU rewrite mode by setting the FMR01 bit in the FMR0 register to “1” (CPU rewrite mode enabled) and is ready to accept software commands. EW mode 0 is selected by setting the FMR11 bit in the FMR1 register to “0”.
Page 326: Register Description
18. Flash Memory Version 18.5 Register Description Figure 18.7 shows the flash memory control register 0 and flash memory control register 1. Figure 18.8 shows the flash memory control register 4. 18.5.1 Flash Memory Control Register 0 (FMR0) •FMR 00 Bit The FMR00 bit indicates the operating state of the flash memory.
Page 327: Flash Memory Control Register 1 (Fmr1)
18. Flash Memory Version 18.5.2 Flash Memory Control Register 1 (FMR1) •FMR11 Bit EW mode 1 is entered by setting the FMR11 bit to 1 (EW mode 1). The FMR11 bit is valid only when the FMR01 bit is set to 1. •FMR16 Bit The combined setting of bits FMR02 and FMR16 enables program and erase in the user ROM area.
Page 328 18. Flash Memory Version Flash Memory Control Register 0 b7 b6 b5 b4 b3 b2 b1 b0 Symbol Address After Reset FMR0 01B7 00000001 Bit Name Function Bit Symbol 0: Busy (during writing or erasing) RY/BY status flag FMR00 1: Ready 0: Disables CPU rewrite mode CPU rewrite mode select bit FMR01...
Page 329 18. Flash Memory Version Flash Memory Control Register 4 b7 b6 b5 b4 b3 b2 b1 b0 Symbol Address After Reset FMR4 01B3 01000000 Bit Symbol Bit Name Function Erase suspend function 0: Disabled FMR40 enable bit 1: Enabled Erase suspend 0: Erase restart FMR41 1: Suspend request...
Page 330 18. Flash Memory Version EW mode 0 operation procedure Rewrite control program Set the FMR01 bit to “1” after writing “0” Single-chip mode (CPU rewrite mode enabled) Set CM0, CM1, and PM1 registers Execute software commands Transfer a rewrite control program to internal RAM Execute the Read Array command area Write “0”...
Page 331 18. Flash Memory Version Low power consumption mode program Transfer a low power internal consumption mode Set the FMR01 bit to “1” after setting “0” program to RAM area (CPU rewrite mode enabled) Set the FMSTP bit to “1” (flash memory stopped. Jump to the low power consumption mode Low power consumption state) program transferred to internal RAM area.
Page 332: Precautions In Cpu Rewrite Mode
18. Flash Memory Version 18.6 Precautions in CPU Rewrite Mode Described below are the precautions to be observed when rewriting the flash memory in CPU rewrite mode. 18.6.1 Operation Speed When the CPU clock source is the main clock, set the CPU clock frequency at 10 MHz or less with the CM06 bit in the CM0 register and the CM17 and CM16 bits in the CM1 register, before entering CPU rewrite mode (EW mode 0 or EW mode 1).
Page 333: Dma Transfer
18. Flash Memory Version 18.6.6 DMA Transfer In EW mode 1, do not generate a DMA transfer while the FMR00 bit in the FMR0 register is set to “0”. (during the auto-programming or auto-erasing). 18.6.7 Writing Command and Data Write the command codes and data to even addresses in the user ROM area. 18.6.8 Wait Mode When entering wait mode, set the FMR01 bit to “0”...
Page 334: Software Commands
18. Flash Memory Version 18.7 Software Commands Read or write 16-bit commands and data from or to even addresses in the user ROM area. When writing a command code, 8 high-order bits (D –D ) are ignored. Table 18.5 Software Commands First bus cycle Second bus cycle Command...
Page 335: Clear Status Register Command (50 )
18. Flash Memory Version 18.7.3 Clear Status Register Command (50 The clear status register command clears the status register to “0”. By writing ‘xx50 ’ in the first bus cycle, and the FMR06 to FMR07 bits in the FMR0 register and SR4 to SR5 bits in the status register are set to “0”.
Page 336: Block Erase
18. Flash Memory Version 18.7.5 Block Erase Auto erase operation (erase and verify) start in the specified block by writing ‘xx20 ’ in the first bus cycle and ‘xxD0 ’ to the highest-order even addresse of a block in the second bus cycle. The FMR00 bit in the FMR0 register indicates whether the auto-erase operation has been completed.
Page 337 18. Flash Memory Version (EW mode 0) Start Interrupt service routine FMR41=1 FMR40=1 Write the command code ‘xx20 ’ FMR46=1? Write ‘xxD0 ’ to the highest-order block address Access Flash Memory FMR00=1? FMR41=0 Return (2,4) Full status check (Interrupt service routine end) Block erase completed (EW mode 1) Start...
Page 338: Status Register
18. Flash Memory Version 18.8 Status Register The status register indicates the operating status of the flash memory and whether or not erase or pro- gram operation is successfully completed. The FMR00, FMR06, and FMR07 bits in the FMR0 register indicate the status of the status register.
Page 339: Full Status Check
18. Flash Memory Version 18.8.4 Full Status Check If an error occurs, the FMR06 to FMR07 bits in the FMR0 register are set to “1”, indicating a specific error. Therefore, execution results can be comfirmed by verifying these status bits (full status check). Table 18.7 lists errors and FMR0 register state.
Page 340 18. Flash Memory Version Full status check FMR06 =1 (1) Execute the clear status register command and set Command the status flag to “0” whether the command is FMR07=1? sequence error entered. (2) Execute the command again after checking that the correct command is entered or the program command or the block erase command is not executed on the protected blocks.
Page 341: Standard Serial I/O Mode
18. Flash Memory Version 18.9 Standard Serial I/O Mode In standard serial I/O mode, the serial programmer supporting the M16C/28 group can be used to rewrite the flash memory user ROM area, while the microcomputer is mounted on a board. For more information about the serial programmer, contact your serial programmer manufacturer.
Page 342 18. Flash Memory Version Table 18.8 Pin Descriptions (Flash Memory Standard Serial I/O Mode) Name Description Apply the voltage guaranteed for Program and Erase to Vcc pin and 0 Power input V to Vss pin. Connect to Vcc pin. RESET Reset input Reset input pin.
Page 343 18. Flash Memory Version BUSY SCLK M16C/28 Group (64-Pin Package) (M16C/28, M16C/28B) (Flash memory version) PLQP0064KB-A(64P6Q-A) Mode setup method Signal Value CNVss Reset Vss to Vcc Connect oscillator circuit NOTES: 1. Set the following, either or both, in serial I/O Mode, while the RESET pin is applied a low-level ("L") signal. -Connect the CE pin to Vcc.
Page 344 18. Flash Memory Version M16C/28 Group (80-Pin Package) (M16C/28, M16C/28B) (Flash memory version) BUSY SCLK PLQP0080KB-A(80P6Q-A) Mode setup method Signal Value CNVss Reset Vss to Vcc Connect oscillator circuit NOTES: 1. Set the following, either or both, in serial I/O Mode, while the RESET pin is applied a low-level ("L") signal. -Connect the CE pin to Vcc.
Page 345: Example Of Circuit Application In Standard Serial I/O Mode
18. Flash Memory Version 18.9.2 Example of Circuit Application in Standard Serial I/O Mode Figure 18.18 shows an example of a circuit application in standard serial I/O mode 1 and Figure 18.19 shows an example of a circuit application in standard serial I/O mode 2. Refer to the user's manual of your serial programmer to handle pins controlled by the serial programmer.
Page 346 18. Flash Memory Version Microcomputer SCLK (CE) TxD output BUSY Monitor output RxD input CNVss (RP) (1) In this example, a selector controls the input voltage applied to CNVss to switch between single-chip mode and standard serial I/O mode. NOTES: 1.
Page 347: Parallel I/O Mode
18. Flash Memory Version 18.10 Parallel I/O Mode In parallel input/output mode, the user ROM can be rewritten by a parallel programmer supporting the M16C/28 group. Contact your parallel programmer manufacturer for more information on the parallel pro- grammer. Refer to the user’s manual included with your parallel programmer for instructions. 18.10.1 ROM Code Protect Function The ROM code protect function prevents the flash memory from being read or rewritten.
Page 348: Electrical Characteristics
19. Electrical Characteristics) 19. Electrical Characteristics The electrical characteristics of the M16C/28 Group Normal-ver. are listed below. Table 19.1 Absolute Maximum Ratings 4 - < < ° 5 ° ° ° ° NOTE: 1. Refer to Tables 1.5 and 1.6 Product Code. page 328...
Page 349 19. Electrical Characteristics Table 19.2 Recommended Operating Conditions " ( ) " L " ) " " ( ) " " ( ) " L " ) " L " ) " l l i l l i l l i l l i l l i l l i...
Page 350 19. Electrical Characteristics) Table 19.3 A/D Conversion Characteristics s t i ± n i l y t i ± ± ± ± ± l a i n i l y t i ± ± ± t s i kΩ µs A ø...
Page 351 19. Electrical Characteristics Table 19.4 Flash Memory Version Electrical Characteristics Program Space and Data Space for U3 and U5, Program Space for U7 and U9 µs ° ) ° ) µs z i l Table 19.5 Flash Memory Version Electrical Characteristics : Data Space for U7 and U9 , 3 ( µs...
Page 352 19. Electrical Characteristics) (1, 3) Table 19.6 Voltage Detection Circuit Electrical Characteristics > h " . " ≤ l a i Table 19.7 Power Supply Circuit Timing Characteristics z i l z i l l l i µs µs µs µs page 332...
Page 353 19. Electrical Characteristics d(P-R) Wait time to stabilize internal supply voltage when power-on d(ROC) td(P-R) td(ROC) Wait time to stabilize internal on-chip oscillator when power- RESET Interrupt for d(R-S) (a) Stop mode release STOP release time (b) Wait mode release d(W-S) Low power dissipation mode wait mode release time...
Page 354 19. Electrical Characteristics) = 5V Table 19.8 Electrical Characteristics " ( ) " µA " ( ) " " ( ) " e i l " ( ) " e i l L " ) " µA L " ) " L "...
Page 355 19. Electrical Characteristics = 5V Table 19.9 Electrical Characteristics (2) l l i l l i µA µA l l i µA µA µA l l i µA ) 2 ( t i a a l l o i t y t i µA ) 2 (...
Page 356 19. Electrical Characteristics) = 5V Timing Requirements = 5V, V = 0V, at Topr = – 20 to 85 C / – 40 to 85 C unless otherwise specified) Table 19.10 External Clock Input (X input) " ( ) " L "...
Page 357 19. Electrical Characteristics = 5V Timing Requirements = 5V, V = 0V, at Topr = – 20 to 85 C / – 40 to 85 C unless otherwise specified) Table 19.11 Timer A Input (Counter Input in Event Counter Mode) Standard Symbol Parameter...
Page 358 19. Electrical Characteristics) = 5V Timing Requirements = 5V, V = 0V, at Topr = – 20 to 85 C / – 40 to 85 C unless otherwise specified) Table 19.17 Timer B Input (Counter Input in Event Counter Mode) Standard Symbol Parameter...
Page 359 19. Electrical Characteristics = 5V Timing Requirements = 5V, V = 0V, at Topr = – 20 to 85 C / – 40 to 85 C unless otherwise specified) Table 19.23 Multi-master I C-Bus Line Standard clock mode High-speed clock mode Symbol Parameter Unit...
Page 360 19. Electrical Characteristics) = 5V XIN input w(H) w(L) c(TA) w(TAH) TAiIN input w(TAL) c(UP) w(UPH) TAiOUT input w(UPL) TAiOUT input (Up/down input) During event counter mode TAiIN input h(TIN-UP) su(UP-TIN) (When count on falling edge is selected) TAiIN input (When count on rising edge is selected) Two-phase pulse input in event counter mode...
Page 361 19. Electrical Characteristics = 5V c(CK) w(CKH) CLKi w(CKL) h(C–Q) TxDi su(D–C) d(C–Q) h(C–D) RxDi w(INL) INTi input w(INH) Figure 19.3. Timing Diagram (2) = 5V HD:STA :STO HD:STA HD:DTA HIGH :DAT :STA Figure 19.4 Timing Diagram (3) page 341...
Page 362 19. Electrical Characteristics) = 3V Table 19.24 Electrical Characteristics " ( ) " " ( ) " µA e i l " ( ) " e i l L " ) " L " ) " µA e i l L "...
Page 363 19. Electrical Characteristics = 3V Table 19.25 Electrical Characteristics (2) l l i l l i µA µA l l i µA µA µA l l i µA ) 2 ( t i a a l l o i t y t i µA ) 2 (...
Page 364 19. Electrical Characteristics) = 3V Timing Requirements = 3V, V = 0V, at Topr = – 20 to 85 C / – 40 to 85 C unless otherwise specified) Table 19.26 External Clock Input (X input) " ( ) " L "...
Page 365 19. Electrical Characteristics = 3V Timing Requirements = 3V, V = 0V, at Topr = – 20 to 85 C / – 40 to 85 C unless otherwise specified) Table 19.27 Timer A Input (Counter Input in Event Counter Mode) Standard Symbol Parameter...
Page 366 19. Electrical Characteristics) = 3V Timing Requirements = 3V, V = 0V, at Topr = – 20 to 85 C / – 40 to 85 C unless otherwise specified) Table 19.33 Timer B Input (Counter Input in Event Counter Mode) Standard Symbol Parameter...
Page 367 19. Electrical Characteristics = 3V Timing Requirements = 3V, V = 0V, at Topr = – 20 to 85 C / – 40 to 85 C unless otherwise specified) Table 19.39 Multi-master I C-Bus Line Standard clock mode High-speed clock mode Symbol Parameter Unit...
Page 368 19. Electrical Characteristics) = 3V XIN input w(H) w(L) c(TA) w(TAH) TAiIN input w(TAL) c(UP) w(UPH) TAiOUT input w(UPL) TAiOUT input (Up/down input) During Event Counter Mode TAiIN input h(TIN-UP) su(UP-TIN) (When count on falling edge is selected) TAiIN input (When count on rising edge is selected) Two-Phase Pulse Input in Event Counter Mode...
Page 369 19. Electrical Characteristics = 3V c(CK) w(CKH) CLKi w(CKL) h(C–Q) TxDi su(D–C) d(C–Q) h(C–D) RxDi w(INL) INTi input w(INH) Figure 19.6 Timing Diagram (2) = 3V HD:STA :STO HD:STA HD:DTA HIGH :DAT :STA Figure 19.7 Timing Diagram (3) page 349...
Page 370: Precautions
20. Precautions 20. Precautions 20.1 SFR 20.1.1 For 80-Pin and 85-Pin Package Set the IFSR20 bit in the IFSR2A register to "1" after reset and set the PACR2 to PACR0 bits in the PACR register to "011 ". 20.1.2 For 64-Pin Package Set the IFSR20bit in the IFSR2A register to "1"...
Page 371: For Flash Memory (128K+4K) Version And Mask Rom Version
20. Precautions Low-Power Consumption Control Register 0 S y m b o l A d d r e s s A f t e r R e s e t 0 0 0 L P C C 0 0 2 1 0 X 0 0 0 0 0 0 1 Function Bit Name...
Page 372: Clock Generation Circuit
20. Precautions 20.2 Clock Generation Circuit 20.2.1 PLL Frequency Synthesizer Stabilize supply voltage so that the standard of the power supply ripple is met. Standard Symbol Unit Parameter Min. Typ. Max. Power supply ripple allowable frequency(V (ripple) Power supply ripple allowable amplitude =5V) p-p(ripple) voltage...
Page 373: Power Control
20. Precautions 20.2.2 Power Control 1. When exiting stop mode by hardware reset, the device will startup using the on-chip oscillator. 2. Set the MR0 bit in the TAiMR register(i=0 to 4) to “0”(pulse is not output) to use the timer A to exit stop mode.
Page 374 20. Precautions 5. Wait until the main clock oscillation stabilization time, before switching the CPU clock source to the main clock. Similarly, wait until the sub clock oscillates stably before switching the CPU clock source to the sub clock. 6. Suggestions to reduce power consumption (a) Ports The processor retains the state of each I/O port even when it goes to wait mode or to stop mode.
Page 375: Protection
20. Precautions 20.3 Protection Set the PRC2 bit to “1” (write enabled) and then write to any address, and the PRC2 bit will be cleared to “0” (write protected). The registers protected by the PRC2 bit should be changed in the next instruction after setting the PRC2 bit to “1”.
Page 376: Interrupts
20. Precautions 20.4 Interrupts 20.4.1 Reading Address 00000 Do not read the address 00000 in a program. When a maskable interrupt request is accepted, the CPU reads interrupt information (interrupt number and interrupt request priority level) from the address 00000 during the interrupt sequence.
Page 377: Int Interrupt
20. Precautions Changing the interrupt source (2,3) Disable interrupts Change the interrupt generate factor (including a mode change of peripheral function) Use the MOV instruction to clear the IR bit to “0” (interrupt not requested) (2,3) Enable interrupts End of change IR bit: A bit in the interrupt control register for the interrupt whose interrupt generate factor is to be changed NOTES:...
Page 378: Rewrite The Interrupt Control Register
20. Precautions 20.4.6 Rewrite the Interrupt Control Register (1) The interrupt control register for any interrupt should be modified in places where no requests for that interrupt may occur. Otherwise, disable the interrupt before rewriting the interrupt control register. (2) To rewrite the interrupt control register for any interrupt after disabling that interrupt, be careful with the instruction to be used.
Page 379: Dmac
20. Precautions 20.5 DMAC 20.5.1 Write to DMAE Bit in DMiCON Register (i = 0, 1) When both of the conditions below are met, follow the steps below. (a) Conditions • The DMAE bit is set to “1” again while it remains set (DMAi is in an active state). •...
Page 380: Timer
20. Precautions 20.6 Timer 20.6.1 Timer A 20.6.1.1 Timer A (Timer Mode) 1. The timer remains idle after reset. Set the mode, count source, counter value, etc. using the TAiMR (i = 0 to 4) register and the TAi register before setting the TAiS bit in the TABSR register to “1” (count starts).
Page 381 20. Precautions 20.6.1.3 Timer A (One-shot Timer Mode) 1. The timer remains idle after reset. Set the mode, count source, counter value, etc. using the TAiMR (i = 0 to 4) register, the TAi register, the ONSF register TA0TGL and TA0TGH bits and the TRGSR register before setting the TAiS bit in the TABSR register to “1”...
Page 382 20. Precautions 20.6.1.4 Timer A (Pulse Width Modulation Mode) 1. The timer remains idle after reset. Set the mode, count source, counter value, etc. using the TAiMR (i = 0 to 4) register, the TAi register, the ONSF register TA0TGL and TA0TGH bits and the TRGSR register before setting the TAiS bit in the TABSR register to “1”...
Page 383: Timer B
20. Precautions 20.6.2 Timer B 20.6.2.1 Timer B (Timer Mode) 1. The timer remains idle after reset. Set the mode, count source, counter value, etc. using the TBiMR (i = 0 to 2) register and TBi register before setting the TBiS bit in the TABSR register to “1” (count starts).
Page 384: Three-Phase Motor Control Timer Function
20. Precautions 6. When a count is started and the first effective edge is input, an indeterminate value is transferred to the reload register. At this time, timer Bi interrupt request is not generated. 7. A value of the counter is indeterminate at the beginning of a count. MR3 may be set to “1” and timer Bi interrupt request may be generated between a count start and an effective edge input.
Page 385: Timer S
20. Precautions 20.7 Timer S 20.7.1 Rewrite the G1IR Register Bits in the G1IR register are not automatically set to 0 (no interrupt requested) even if a requested inter- rupt is acknowledged. Set each bit to 0 by program after the interrupt requests are verified. The IC/OC interrupt is generated when any bit in the G1IR register is set to 1 (interrupt requested) after all the bits are set to 0.
Page 386: Rewrite The Icociic Register
20. Precautions 20.7.2 Rewrite the ICOCiIC Register When the interrupt request to the ICOCiIC register is generated during the instruction process, the IR bit may not be set to "1" (interrupt requested) and the interrupt request may not be acknowledged. At that time, when the bit in the G1IR register is held to "1"...
Page 387: Serial I/O
20. Precautions 20.8 Serial I/O 20.8.1 Clock-Synchronous Serial I/O 20.8.1.1 Transmission/reception _______ ________ 1. With an external clock selected, and choosing the RTS function, the output level of the RTSi pin goes to “L” when the data-receivable status becomes ready, which informs the transmission side ________ that the reception has become ready.
Page 388: Uart Mode
20. Precautions 20.8.2 UART Mode 20.8.2.1 Special Mode 1 (I C bus Mode) When generating start, stop and restart conditions, set the STSPSEL bit in the U2SMR4 register to “0” and wait for more than half cycle of the transfer clock before setting each condition generate bit (STAREQ, RSTAREQ and STPREQ) from “0”...
Page 389: A/D Converter
20. Precautions 20.9 A/D Converter 1. Set ADCON0 (except bit 6), ADCON1, ADCON2 and ADTRGCON registers when A/D conversion is stopped (before a trigger occurs). 2. When the VCUT bit in ADCON1 register is changed from “0” (Vref not connected) to “1” (Vref con- nected), start A/D conversion after passing 1 µs or longer.
Page 390 20. Precautions 8. If the CPU reads the AD register i (i = 0 to 7) at the same time the conversion result is stored in the AD register i after completion of A/D conversion, an incorrect value may be stored in the AD register i. This problem occurs when a divide-by-n clock derived from the main clock or a subclock is selected for CPU clock.
Page 391: Multi-Master I 2 C Bus Interface
20. Precautions 20.10 Multi-master I C bus Interface 20.10.1 Writing to the S00 Register When the start condition is not generated, the SCL pin may output the short low-signal ("L") by setting the S00 register. Set the register when the SCL pin outputs an "L" signal. 20.10.2 AL Flag When the arbitration lost is generated and the AL flag in the S10 register is set to "1"...
Page 392: Programmable I/O Ports
20. Precautions 20.11 Programmable I/O Ports _____ 1. If a low-level signal is applied to the SD pin when the IVPCR1 bit in the TB2SC register is set to “1” _____ (three-phase output forcible cutoff by input on SD pin enabled), the P7 to P7 , P8 and P8...
Page 393: Electric Characteristic Differences Between Mask Rom And Flash Memory Version
20. Precautions 20.12 Electric Characteristic Differences Between Mask ROM and Flash Memory Version Flash memory version and mask ROM version may have different characteristics, operating margin, noise tolerated dose, noise width dose in electrical characteristics due to internal ROM, different layout pattern, etc.
Page 394: Mask Rom Version
20. Precautions 20.13 Mask ROM Version 20.13.1 Internal ROM Area In the masked ROM version, do not write to internal ROM area. Writing to the area may increase power consumption. 20.13.2 Reserved Bit The b3 to b0 in addresses 0FFFFF are reserved bits.
Page 395: Flash Memory Version
20. Precautions 20.14 Flash Memory Version 20.14.1 Functions to Inhibit Rewriting Flash Memory Rewrite ID codes are stored in addresses 0FFFDF , 0FFFE3 , 0FFFEB , 0FFFEF , 0FFFF3 , 0FFFF7 and 0FFFFB . If wrong data are written to theses addresses, the flash memory cannot be read or written in standard serial I/O mode.
Page 396: Interrupts
20. Precautions 20.14.9 Interrupts EW Mode 0 • Any interrupt which has a vector in the variable vector table can be used providing that its vector is transferred into the RAM area. _______ • The NMI and watchdog timer interrupts can be used because the FMR0 register and FMR1 register are initialized when one of those interrupts occurs.
Page 397: Definition Of Programming/Erasure Times
20. Precautions 20.14.14 Definition of Programming/Erasure Times "Number of programs and erasure" refers to the number of erasure per block. If the number of program and erasure is n (n=100 1,000 10,000) each block can be erased n times. For example, if a 2K byte block A is erased after writing 1 word data 1024 times, each to a different address, this is counted as one program and erasure.
Page 398: Noise
20. Precautions 20.15 Noise Connect a bypass capacitor (approximately 0.1µF) across the V and V pins using the shortest and thicker possible wiring. Figure 20.6 shows the bypass capacitor connection. M16C/28 Group Connecting Pattern Connecting Pattern Bypass Capacitor Figure 20.6 Bypass Capacitor Connection 20.15.1 Trace of Print Board (85-pin Package) Creat a layout with thick lines as shown in Figure 20.7 for the trace around clock pins on the print board to avoid the effect of noise input from other pins to the clock pins (X...
Page 399: Instruction For A Device Use
20. Precautions 20.16 Instruction for a Device Use When handling a device, extra attention is necessary to prevent it from crashing during the electrostatic discharge period. page 379...
Page 400: Appendix 1. Package Dimensions
Appendix 1. Package Dimensions Appendix 1. Package Dimensions JEITA Package Code RENESAS Code Previous Code MASS[Typ.] P-LQFP64-10x10-0.50 PLQP0064KB-A 64P6Q-A / FP-64K / FP-64KV 0.3g NOTE) 1. DIMENSIONS "*1" AND "*2" DO NOT INCLUDE MOLD FLASH. DIMENSION "*3" DOES NOT INCLUDE TRIM OFFSET.
Page 401 Appendix 1. Package Dimensions JEITA Package Code RENESAS Code Previous Code MASS[Typ.] P-TFLGA85-7x7-0.65 PTLG0085JB-A 85F0G 0.1g S AB Dimension in Millimeters Reference Index mark Symbol Min Nom Max (Laser mark) Index mark 0.15 0.20 1.05 0.65 0.31 0.35 0.39 0.39 0.43 0.47 0.08...
Page 402: Appendix 2. Functional Comparison
Appendix 2. Functional Comparison Appendix 2. Functional Comparison Appendix 2.1 Difference between M16C/28 Group Normal-ver. and M16C/28 Group T-ver./V-ver. o i t ) . r / . r ) . r o i t o i t a l i o i t o i t s t i...
Page 403: Appendix 2.2 Difference Between M16C/28 Group And M16C/29 Group (Normal-Ver.)
Appendix 2. Functional Comparison Appendix 2.2 Difference between M16C/28 Group and M16C/29 Group (Normal-ver.) ) . r ) . r a l i s t i a l i ) t i ) t i t s i c t i a l i ) t i t s i...
Page 404: Register Index
Register Index Register Index G1IE1 145 G1IR 144 AD0 to AD7 221 G1PO0 to G1PO7 142 ADCON0 to ADCON2 219 G1POCR0 to G1POCR7 141 ADIC 73 G1TM0 to G1TM7 141 ADSTAT0 221 G1TMCR0 to G1TMCR7 140 ADTRGCON 220 G1TPR6 to G1TPR7 140 AIER 85 ICOC0IC 73 BCNIC 73...
Page 405 Register Index PD0 to PD3 289 TA4 127 PD6 to PD10 289 TA41 127 PDRF 134 TA4MR 130 PLC0 50 TABSR 101, 115, 129 PM2 49 TB0 to TB2 115 PRCR 66 TB0IC to TB2IC 73 PUR0 to PUR2 291 TB0MR to TB2MR 114 TB2 129 TB2MR 130...
Page 406 REVISION HISTORY M16C/28 Group (M16C/28, M16C/28B) Hardware Manual Rev. Date Description Page Summary New Document 0.60 Feb., 04 All Pages New chapters added 1.00 Jul., 05 Chapter, Table and Figure numbers modified Words standardized: On-chip oscillator, A/D converter and D/A converter, EW mode 0,1, IEBus, I C bus Description of T-ver./V-ver.
Page 407 REVISION HISTORY M16C/28 Group (M16C/28, M16C/28B) Hardware Manual Rev. Date Description Page Summary TB0 to TB2, TB0MR to TB2MR, U0BRG, U0TB, U0RB, U1BRG, U1TB, U1RB, AD0 to AD7, ADTRGCON, ADSTAT0, ADCON0, P0 to P3, and P6 to P10 regis- ters revised •...
Page 408 REVISION HISTORY M16C/28 Group (M16C/28, M16C/28B) Hardware Manual Rev. Date Description Page Summary • Figure 9.5 Time Required for Executing Interrupt Sequence note 2 added • Figure 9.9 Hardware Interrupt Priority Watchdog timer added ______ • 9.6 INT Interrupt modified ______ •...
Page 409 REVISION HISTORY M16C/28 Group (M16C/28, M16C/28B) Hardware Manual Rev. Date Description Page Summary • Figure 13.5 G1TMCR0 to G1TMCR7 Registers, and G1TPR6 to G1TPR7 Registers Values afte reset modified, G1TPR6 to G1TPR7 Registers: note 2 modified • Figure 13.6 G1TM0 to G1TM7 Registers, and G1POCR0 to G1POCR7 Reg- isters G1POCR0 to G1POCR7 Registers: Note 3 and 4 added •...
Page 410 REVISION HISTORY M16C/28 Group (M16C/28, M16C/28B) Hardware Manual Rev. Date Description Page Summary • Table 14.4 P6 Pin Functions Note 1 added • Figure 14.10 Typical transmit/receive timings in clock synchronous serial I/ O mode Example of receive timing: figure modified •...
Page 411 REVISION HISTORY M16C/28 Group (M16C/28, M16C/28B) Hardware Manual Rev. Date Description Page Summary • Figure 15.13 ADCON0 to ADCON2 Registers in Repeat Mode 0 ADCON2 register: b2-b1 function modified • Figure 15.15 ADCON0 to ADCON2 Registers in Repeat Mode 1 ADCON2 register: b2-b1 function modified •...
Page 412 REVISION HISTORY M16C/28 Group (M16C/28, M16C/28B) Hardware Manual Rev. Date Description Page Summary • 16.5.8 Bit 7: Communication mode select bit (master/slave select bit: MST) modified • 16.6.5 Bits 6, 7: I2C System Clock Select Bits ICK0, ICK1 modified • Figure 16.20 Address data communication format moved •...
Page 413 REVISION HISTORY M16C/28 Group (M16C/28, M16C/28B) Hardware Manual Rev. Date Description Page Summary Electrical Characteristics Description of T-ver. and V-ver. deleted • Table 19.1 Absolute Maximum Ratings Condition of Pd modified, Parameter / condition/value of Topr modified • Table 19.2 Recommended Operating Conditions Standard values of V modified, parameter of V and V modified, note 4...
Page 414 REVISION HISTORY M16C/28 Group (M16C/28, M16C/28B) Hardware Manual Rev. Date Description Page Summary ______ • 20.5.3 NMI Interrupt 6. information added ______ • 20.5.5 INT Interrupt 3. information added • 20.7.1.3 Timer A (One-shot Timer Mode) 6. information added • 20.7.1.4 Timer B (Pulse Width Modulation Mode) 2. information modified •...
Page 415 REVISION HISTORY M16C/28 Group (M16C/28, M16C/28B) Hardware Manual Rev. Date Description Page Summary • Figure 1.3 Produt Numbering System is modified • Table 1.4 Product Code None-lead free packages are deleted • Table 1.5 Product Code - 85-pin Devise is added with note 1 •...
Page 416 REVISION HISTORY M16C/28 Group (M16C/28, M16C/28B) Hardware Manual Rev. Date Description Page Summary Timer • Figure 12.28 IDB0 Register, IDB1 Register, DTT Register, and ICTB2 Regis- ter Information of bit 7 and 6 is changed Timer S • Figure 13.5 G1TMCR0 to G1TMCR7 Registers Note 4 is modified 135-142 •...
Page 417 REVISION HISTORY M16C/28 Group (M16C/28, M16C/28B) Hardware Manual Rev. Date Description Page Summary • Figure 18.4 Flash Memory Block Digram (ROM capacity 128K byte) is added • Figure 18.5 ROMCP Address is modified • Table 18.3 EW Mode 0 and EW Mode 1 Note 2 mark is modified •...
Page 418 REVISION HISTORY M16C/28 Group (M16C/28, M16C/28B) Hardware Manual Rev. Date Description Page Summary module, and CRC calculation in M16C/28 (Normal-ver.) changed • Appendix 2.3 Difference between M16C/28 and M16C/29 Groups (T-ver./V- ver.) Information of CAN module changed 1.11 Apr., 06 Overview 2, 3 •...
Page 419 REVISION HISTORY M16C/28 Group (M16C/28, M16C/28B) Hardware Manual Rev. Date Description Page Summary • 7.4 PLL Clock Description regarding use of M16C/28B partially added • Table 7.2 Example for Setting PLL Clock Frequencies Description regarding use of M16C/28B partially added •...
Page 420 REVISION HISTORY M16C/28 Group (M16C/28, M16C/28B) Hardware Manual Rev. Date Description Page Summary • Table 13.11 Pin Setting for Time Measurement and Waveform Generating Functions Description of port direction modified Serial I/O • Figure 14.1 Block Diagram of UARTi Partially modified •...
Page 421 REVISION HISTORY M16C/28 Group (M16C/28, M16C/28B) Hardware Manual Rev. Date Description Page Summary • Table 18.7 Errors and FMR0 Register Status Register name modified • Table 18.8 Pin Descriptions Description of P9 modified Electrical Characteristics • Table 19.2 Recommended Operating Conditions Values added, figures modified and added •...
Page 422 RENESAS 16-BIT CMOS SINGLE-CHIP MICROCOMPUTER HARDWARE MANUAL M16C/28 Group (M16C/28, M16C/28B) Publication Date: Rev.0.60 Feb. 2004 Rev.2.00 Jan. 31, 2007 Published by: Sales Strategic Planning Div. Renesas Technology Corp. © 2007. Renesas Technology Corp., All rights reserved. Printed in Japan.
Page 423 M16C/28 Group (M16C/28, M16C/28B) Hardware Manual 2-6-2, Ote-machi, Chiyoda-ku, Tokyo, 100-0004, Japan...

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Renesas M16C FAMILY series Hardware Manual

1 Overview

2 Central Processing Unit (CPU)

3 Memory

4 Special Function Register (SFR)

5 Reset

6 Processor Mode

7 Clock Generation Circuit

8 Protection

9 Interrupts

10 Watchdog Timer

11 Dmac

12 Timer

13 Timer S

14 Serial I/O

15 A/D Converter

16 Multi-Master I C Bus Interface

17 Programmable I/O Ports

18 Flash Memory Version

19 Electrical Characteristics

20 Precautions

Appendix 1. Package Dimensions

Appendix 2. Functional Comparison

Appendix 2.1 Difference between M16C/28 Group Normal-Ver. and M16C/28 Group T-Ver./V-Ver

Appendix 2.2 Difference between M16C/28 Group and M16C/29 Group (Normal-Ver.)

Register Index

Quick Links

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Summary of Contents for Renesas M16C FAMILY series