Renesas M16C/50 Series User Manual page 577

M16C/5L Group, M16C/56 Group
22.3.10.4 Slave Reception
The slave reception is described in this section. The initial settings described in 222.3.10.1 "Initial
Settings" are assumed to be completed. Figure 22.19 shows the example of slave reception. The
following programs (A) to (C) are executed at (A) to (C) in Figure 22.19, respectively.
SCLMM
SDAMM
IR bit in the
IICIC register
Figure 22.19 Example of Slave Reception
(A) Slave receive is started.
2
(In I C-bus interrupt routine)
(1) Check the value of the S10 register. When the TRX bit is 0, the I
mode.
(2) Write dummy data to the S00 register.
(B) Data reception 1
2
(In I C-bus interrupt routine)
(1) Read the received data from the S00 register.
(2) Set the ACKBIT bit in the S20 register to 0 (ACK presents) because the data is not the last one.
(3) Write dummy data to the S00 register.
(C) Data reception 2
2
(In I C-bus interrupt routine)
(1) Read the received data from the S00 register.
(2) Set the ACKBIT bit in the S20 register to 1 (no ACK presents) because the data is the last one.
(3) Write dummy data to the S00 register.
R01UH0127EJ0110 Rev.1.10
Sep 01, 2011
S: Start condition
P: Stop condition
m
Slave address
S
W
(7 bits)
A: ACK R: Read
A: NACK W: Write
s m s
Data
A A
(8 bits)
Set to 0 by interrupt request acceptance or by program
(A) Start of slave reception
22. Multi-master I
m: Master outputs to SDA
s: Slave outputs to SDA
m s
Data
A/A
(8 bits)
(B) Data reception 1
(C) Data reception 2
Completion of slave reception
2
C interface is in slave receive
Page 540 of 803
2
C-bus Interface
m
P