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M16C/5L Group, M16C/56 Group
28.17.2.3 Reception
In clock synchronous serial I/O mode, a shift clock is generated by activating a transmitter. Set the
UARTi-associated registers for a transmit operation even if the MCU is used for a receive operations
only. Dummy data is output from the TXDi pin (i = 0 to 4) while receiving.
When an internal clock is selected, a shift clock is generated by setting the TE bit in the UiC1 register
to 1 (transmission enabled) and placing dummy data in the UiTB register. When an external clock is
selected, set the TE bit to 1 (transmission enabled), set dummy data in the UiTB register, and input
an external clock to the CLKi pin to generate a shift clock.
If data is received consecutively, an overrun error occurs when the RI bit in the UiC1 register is 1
(data present in the UiRB register) and the next receive data is received in the UARTi receive
register. Then, the OER bit in the UiRB register becomes 1 (overrun error occurred). At this time, the
UiRB register is undefined. When an overrun error occurs, program the transmitting and receiving
sides to retransmit the previous data. If an overrun error occurs again, the IR bit in the SiRIC register
remains unchanged.
To receive data consecutively, set dummy data in the low-order byte in the UiTB register for each
receive operation.
If the reception is started while an external clock is selected and the TXEPT bit in the UiC0 register is
1 (no data present in transmit register), meet the last requirement at either of the timings below.
External clock level:
•
The CKPOL bit in the UiC0 register is 0 (transmit data is output at the falling edge of
transmit/receive clock and receive data is input at the rising edge) and the external clock is high.
•
The CKPOL bit is 1 (transmit data is output at the rising edge of transmit/receive clock and receive
data is input at the falling edge) and the external clock is low.
Requirements to start reception (in no particular order):
•
The RE bit in the UiC1 register is 1 (reception enabled).
•
The TE bit in the UiC1 register is 1 (transmission enabled).
•
The TI bit in the UiC1 register is 0 (data present in the UiTB register).
28.17.3 Special Mode 1 (I
28.17.3.1 Generating Start and Stop Conditions
(Technical update number: TN-16C-130A/EA)
When generating start, stop, and restart conditions, set the STSPSEL bit in the U2SMR4 register to 0
and wait for more than a half cycle of the transmit/receive clock. Then set each condition generation
bit (STAREQ, RSTAREQ, and STPREQ) from 0 to 1.
28.17.3.2 IR Bit
Set the following bits first, and then set the IR bit in each UART2 interrupt control register to 0
(interrupt not requested).
Bits SMD2 to SMD0 in the U2MR register, the IICM bit in the U2SMR register,
the IICM2 bit in the U2SMR2 register, the CKPH bit in the U2SMR3 register
R01UH0127EJ0110 Rev.1.10
Sep 01, 2011
2
C Mode)
28. Usage Notes
Page 790 of 803
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