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M16C/5L Group, M16C/56 Group
CM10 = 1
(stop mode)
WAIT instruction
RESET
Software reset
NMI
PM24
Interrupt request level determine output
Watchdog timer reset
Oscillator stop detect reset
Voltage monitor 0 reset
Voltage monitor 2 reset
Voltage monitor 2 interrupt
CM00 to CM04, CM05 to CM07: Bits in the CM0 register
CM10, CM11, CM14, CM16, CM17: Bits in the CM1 register
PCLK5: Bit in the PCLKR register
CM21, CM27: Bits in the CM2 register
PM24: Bit in the PM2 register
FRA00, FRA01: Bits in the FRA1 register
FRA20 to FRA22: Bits in the FRA2 register
Oscillator Stop/Restart Detector
Clock edge
detector,
Main
pulse generator
Clock
for charge/
discharge control
PLL Frequency Synthesizer
Main
Clock
Figure 8.1
System Clock Generator
R01UH0127EJ0110 Rev.1.10
Sep 01, 2011
Sub clock oscillator
XCIN
XCOUT
CM04
40 MHz
FRA00
on-chip
oscillator
125 kHz
fOCO-S
CM14
on-chip
oscillator
Main clock
S
Q
XIN
XOUT
R
Main clock
oscillator
CM05
S
Q
R
CM27 = 0
Charge/
discharge
circuit
CM27 = 1
1/32 or 1/48
Phase
comparator
Reference
clock divider
I/O ports
Sub clock
fC
1/32
FRA22 to FRA20
1/2
1/2
1/2
110b
010b
fOCO-F
000b
FRA01
1
Oscillator
stop/restart
0
detector
PLL frequency
synthesizer
CM21
1
PLL clock
0
CM11
1
0
CM02
a
1/2
1/2
1/2
1/4
CM06 = 0
CM06 = 0
CM17 to CM16
CM17 to CM16
= 10b
= 01b
CM06 = 0, CM17 to CM16 = 00b
Reset
generator
Oscillator stop/
restart detect
interrupt
generator
Charge
pump
8. Clock Generator
CM01 to CM00 = 00b, PCLK5 = 0
CM01 to CM00 = 01b, PCLK5 = 0
CM01 to CM00 = 10b, PCLK5 = 0
f8
CM01 to CM00 = 00b,
CM01 to CM00 = 11b, PCLK5 = 0
PCLK5 = 1
f32
fOCO40M
fC
fC32
fOCO-F
fOCO-S
Main clock
f1
CM07
b
c
1
d
a
Divider
0
b
1/2
1/2
1/2
1/32
1/8
1/16
CM06 = 0
CM17 to CM16 = 11b
CM06 = 1
Detail of Divider
Oscillator stop
detect reset
Oscillator stop/
restart detect
interrupt signal
CM21 switch signal
Divider
Voltage
control
oscillator
(VCO)
Internal
lowpass filter
CLKOUT
Peripheral
function
clock
CPU clock
BCLK
c
d
PLL clock
Page 91 of 803
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